Protection for ethernet physical layer

Patent metadata

Field	Value
Publication number	US-11416332-B2
Application number	US-202117187719-A
Country	US
Kind code	B2
Filing date	Feb 26, 2021
Priority date	Mar 27, 2020
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

Disclosed embodiments include an Ethernet PHY device comprising a serial communication interface adapted to be coupled to a microcontroller, a register set having registers, and a checksum generator circuit coupled to the register set and configured to calculate a current checksum. The embodiment also includes a checksum register that is coupled to the checksum generator and is configured to store the current checksum. It further includes a checksum checker that is coupled to the checksum generator, the checksum register and the microcontroller, and is configured to compare a previous value of the checksum to the current checksum and, responsive to the previous value being different than the current checksum, send an error report to the microcontroller. The embodiment also includes a trigger circuit coupled to the checksum generator configured to send a checksum start signal to the checksum generator.

First claim

What is claimed is:

1. An Ethernet PHY device comprising:
a serial communication interface adapted to be coupled to a microcontroller;
a register set having one or more registers;
a checksum generator circuit coupled to the register set and configured to calculate a current checksum of at least some of the registers;
a checksum register coupled to the checksum generator and configured to store the current checksum;
a checksum checker coupled to the checksum generator, the checksum register and the microcontroller, and configured to compare a previous value of the checksum to the current checksum and, responsive to the previous value being different than the current checksum, send an error report to the microcontroller; and
a trigger circuit having inputs and having an output coupled to the checksum generator, wherein the trigger circuit is configured to send a checksum start signal to the checksum generator in response to receiving an active signal at an input.

2. The device of claim 1 , wherein the serial communication interface is adapted to be coupled to the microcontroller by Management Data Input/Output (MDIO).

3. The device of claim 1 , including an electrostatic discharge (ESD) event sense detector configured to provide an ESD trigger signal to one of the trigger circuit inputs.

4. The device of claim 1 , wherein the trigger circuit inputs include a software trigger input.

5. The device of claim 1 , wherein the trigger circuit inputs include a link loss trigger input configured to provide an active signal if a link loss is detected.

6. The device of claim 1 , wherein the trigger circuit inputs include a software quality index (SQI) input configured to provide an active signal if an SQI drops below an SQI threshold.

7. The device of claim 1 , wherein the trigger circuit inputs include a self-test trigger configured to initiate a self-test sequence.

8. The device of claim 7 , wherein the self-test sequence includes:
a checksum start signal sent by the trigger circuit to the checksum generator;
a self-test checksum generated by the checksum generator responsive to the checksum start signal, wherein the self-test checksum is a checksum of the registers with a fail bit added; and
a failure indication sent by the checksum checker indicating that the self-test checksum does not match the current checksum.

9. A method for detecting a data corruption using hardware in an Ethernet PHY device, comprising:
powering up the Ethernet PHY device;
initializing the PHY device and loading a register image into one or more registers within the PHY device;
reading the registers using a checksum generator in the PHY device;
generating, using the checksum generator, an initial checksum of the registers;
storing the initial checksum in a checksum register in the PHY device;
initiating a check of the registers by the checksum generator reading the registers;
generating, by the checksum generator, a current checksum of the registers; and
comparing the current checksum to the initial checksum to verify that they match.

10. The method of claim 9 , wherein if the current checksum and the initial checksum do not match, an error is reported to a microcontroller unit coupled to the device.

11. The method of claim 9 , wherein if the current checksum and the initial checksum do not match, the register image is reloaded to the registers.

12. The method of claim 9 , wherein if the current checksum and the initial checksum do not match, a system reset is performed.

13. The method of claim 9 , wherein the initiating a check of the registers is in response to a link loss.

14. The method of claim 9 , wherein the initiating a check of the registers is in response to an electrostatic discharge (ESD) event.

15. The method of claim 9 , wherein the initiating a check of the registers is in response to a reduction in a software quality index (SQI).

16. An automotive network transceiver adapted to be coupled to a processor at a transceiver input, the transceiver comprising:
registers coupled to the transceiver input and adapted to store a copy of data stored in the processor;
a checksum generator coupled to the registers, the checksum generator having a checksum output and configured to perform a checksum operation on a portion of the registers;
a checksum register coupled to the checksum output; and
a checksum checker connected to the checksum generator and the checksum register, the checksum checker configured to compare the checksum output to a previous checksum output, and generate an error in response to the checksum output being different than the previous checksum output.

17. The device of claim 16 , including a trigger circuit having inputs and having an output coupled to the checksum generator, wherein the trigger circuit is configured to send a checksum start signal to the checksum generator in response to receiving an active signal at an input.

18. The device of claim 17 , wherein the trigger circuit inputs include a link loss trigger input configured to provide an active signal if a link loss is detected.

19. The device of claim 17 , wherein the trigger circuit inputs include a software quality index (SQI) input configured to provide an active signal if an SQI drops below an SQI threshold.

20. The device of claim 17 , wherein the trigger circuit inputs include a software trigger input.

Assignees

• Texas Instruments Inc

Inventors

• Eckhardt Ralf
• Pimentel Ross Anthony

Classifications

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title