Instruction execution method and instruction execution device

Patent metadata

Field	Value
Publication number	US-11416255-B2
Application number	US-202016813947-A
Country	US
Kind code	B2
Filing date	Mar 10, 2020
Priority date	Jun 19, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

An instruction execution method suitable for being executed by a processor is provided. The first processor comprises a register alias table (RAT) and a reservation station. The instruction execution method includes: a register alias table receives a first micro-instruction and a second micro-instruction and issues the first micro-instruction and the second micro-instruction to the reservation station; and the reservation station assigns one of a plurality of execution units to execute the first micro-instruction, according to the first specific message of the first micro-instruction; and the reservation station assigns one of the execution units to execute the second micro-instruction, according to the second specific message of the second micro-instruction. When the reservation station determines that the execution units assigned for the first micro-instruction and the second micro-instruction are the same, the reservation station indicates that the second micro-instruction depends on the first micro-instruction.

First claim

What is claimed is:

1. An instruction execution method, suitable for being executed by a processor, wherein a first processor comprises a register alias table (RAT) and a reservation station, and the instruction execution method comprises:
receiving a first micro-instruction and a second micro-instruction by the register alias table, and issuing the first micro-instruction and the second micro-instruction to the reservation station by the register alias table, wherein the first micro-instruction is a preceding micro-instruction of the second micro-instruction; and
assigning by the reservation station one of a plurality of execution units to execute the first micro-instruction, according to a first specific message of the first micro-instruction; and assigning by the reservation station one of the execution units to execute the second micro-instruction, according to a second specific message of the second micro-instruction;
wherein when the reservation station determines that the execution units assigned for the first micro-instruction and the second micro-instruction are the same, the reservation station indicates that the second micro-instruction depends on the first micro-instruction;
wherein when the reservation station assigns the first micro-instruction to be dispatched by a first dispatch port of the reservation station for execution, the reservation station records a message corresponding to the first micro-instruction on a first scoreboard corresponding to the first dispatch port;
wherein, when the reservation station assigns the second micro-instruction to be dispatched by the first dispatch port for execution, and the reservation station finds that the first scoreboard includes a message corresponding to the first micro-instruction, the reservation station indicates the second micro-instruction depends on the first micro-instruction;
wherein, when the reservation station assigns the second micro-instruction to be dispatched by a second dispatch port of the reservation station for execution, the reservation station records another message corresponding to the second micro-instruction on a second scoreboard corresponding to the second dispatch port.

2. The instruction execution method of claim 1 , wherein the first specific message and the second specific message represent instruction types of the first micro-instruction and the second micro-instruction respectively.

3. The instruction execution method of claim 2 , wherein when the instruction types of the first micro-instruction and the second micro-instruction are the same, the reservation station assigns the same execution unit as the first micro-instruction for the second micro-instruction.

4. The instruction execution method of claim 2 , wherein when the instruction types of the first micro-instruction and the second micro-instruction are the same, the reservation station assigns one of the execution units for the first micro-instruction and the second micro-instruction in a round robin manner.

5. The instruction execution method of claim 1 , wherein the reservation station determines whether the execution units assigned by the reservation station for the first micro-instruction and the second micro-instruction are the same according to whether a dispatch port corresponding to the execution unit assigned by the reservation station for the second micro-instruction includes a message corresponding to the first micro-instruction.

6. The instruction execution method of claim 1 , wherein the step in which the reservation station indicates that the second micro-instruction depends on the first micro-instruction further comprises:
updating, by the reservation station, a first dependency indicator value corresponding to the second micro-instruction according to a reservation-station matrix-index value of the first micro-instruction.

7. The instruction execution method of claim 1 , wherein the step in which the reservation station indicates that the second micro-instruction depends on the first micro-instruction further comprises:
updating, by the reservation station, at least one second dependency indicator value corresponding to the second micro-instruction according to at least one source operand of the second micro-instruction; and
performing, by the reservation station, an OR operation on the first dependency indicator value and the second dependency indicator value to obtain a dependency region value corresponding to the second micro-instruction.

8. The instruction execution method of claim 1 , further comprising:
after the first micro-instruction is executed, the position corresponding to the first micro-instruction in a dependency region value corresponding to the second micro-instruction is cleared;
when the reservation station determines that all the positions of the dependency region value corresponding to the second micro-instruction are cleared, determining whether the second micro-instruction is the oldest of all micro-instructions assigned to be executed by the assigned execution unit according to the value of an age domain and the value of a port domain corresponding to the second micro-instruction;
when the second micro-instruction is the oldest of all micro-instructions assigned to be executed by the assigned execution unit, the second micro-instruction is dispatched by the reservation station to the assigned execution unit to execute.

9. The instruction execution method of claim 8 , wherein the position corresponding to the first micro-instruction in the dependency region value corresponding to the second micro-instruction is determined by the reservation-station matrix-index value of the first micro-instruction.

10. The instruction execution method of claim 1 , wherein the reservation station further comprises a reservation-station matrix, the reservation-station matrix comprises a plurality of entries, and each entry comprises a dependency domain, an age domain, and a port domain corresponding to a micro-instruction.

11. An instruction execution device, comprising:
a reservation station; and
a register alias table, configured to receive a first micro-instruction and a second micro-instruction, and to issue the first micro-instruction and the second micro-instruction to the reservation station, wherein the first micro-instruction is a preceding micro-instruction of the second micro-instruction;
wherein the reservation station assigns one of the execution units to execute the first micro-instruction according to a first specific message of the first micro-instruction, and assigns one of the execution units to execute the second micro-instruction according to a second specific message of the second micro-instruction;
wherein when the reservation station determines that the execution units assigned for the first micro-instruction and the second micro-instruction are the same, the reservation station indicates that the second micro-instruction depends on the first micro-instruction;
wherein when the reservation station assigns the first micro-instruction to be dispatched by the first dispatch port of the reservation station for execution, the reservation station records a message corresponding to the first micro-instruction on the first scoreboard corresponding to the first dispatch port;
wherein, when the reservation station assigns the second micro-instruction to be dispatched by the first dispatch port for execution, and the reservation station finds that the first scoreboard includes a message corresponding to the first micro-instruction, the reservation station indicates the second micro-instruction depends on the first micro-instruction;
wherein, when the reservation station assigns the second micro-instruction to

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Zou Penghao
• Song Chen-Chen
• Zhang kang-kang
• Wang Jianbin

Classifications

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/223 Primary

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/28

  Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title