AD converter device and millimeter wave radar system

Patent metadata

Field	Value
Publication number	US-11415666-B2
Application number	US-201916585924-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Nov 22, 2018
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A MASH type sigma delta AD converter includes a modulator, an analog filter filtering an extraction signal obtained by extracting a probe signal and an quantization error generated in a quantizer within a sigma delta modulator, a low speed AD converter performing an AD conversion of an output signal of the analog filter, a first adaptive filter searching for a transfer function of the sigma delta modulator, a second adaptive filter searching for a transfer function from an output of the modulator to the low speed AD converter via the analog filter, and a noise cancellation circuit cancelling the probe signal and the quantization error included in an output signal of the quantizer using the search results by the first and second adaptive filters.

First claim

What is claimed is:

1. A MASH (Multi stAge Noise SHaping) type sigma delta AD converter device comprising:
a probe signal generation circuit for generating a probe signal;
a first modulator including a first analog integrator configured with an analog circuit and a first quantizer for quantizing an addition signal obtained by adding the probe signal and an output signal of the first analog integrator;
an analog filter for filtering an extraction signal obtained by extracting the probe signal and a quantization error generated in the first quantizer;
a first AD converter for converting an output signal of the analog filter from an analog signal to a digital signal, the first AD converter operating at an operation frequency lower than an operation frequency of the first modulator;
a first adaptive filter for searching for a first transfer function which is a transfer function of the first modulator by observing an output signal of the first quantizer in accordance with the probe signal;
a second adaptive filter for searching for a second transfer function which is a transfer function from an output of the first modulator to the first AD converter via the analog filter by observing an output signal of the first AD converter in accordance with the probe signal; and
a noise cancellation circuit for canceling the quantization error and the probe signal included in the output signal of the first quantizer using the search result of the first adaptive filter and the search result of the second adaptive filter.

2. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the analog filter is a low pass filter.

3. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the analog filter is an operational amplifier feedback type active filter.

4. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the analog filter is a Gm-C filter.

5. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the analog filter is a discrete time type filter.

6. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the analog filter includes a plurality of discrete time type filters arranged in parallel, and
wherein the plurality of discrete time type filters are configured to filter at different timings.

7. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the analog filter is configured to be able to adjust a frequency characteristic in accordance with the search result of the second adaptive filter.

8. The MASH type sigma delta AD converter device according to claim 7 ,
wherein the analog filter includes a capacitive element configured to be able to adjust a capacitance value for determining the frequency characteristic in accordance with the search results of the second adaptive filter.

9. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the first AD converter is a nyquist AD converter.

10. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the first AD converter is a successive approximation AD converter, and
wherein the analog filter is configured using a capacitive element formed in the first AD converter.

11. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the first AD converter includes a plurality of successive approximation AD converters arranged in parallel,
wherein the analog filter includes a plurality of discrete time type filters arranged in parallel,
wherein the plurality of discrete time type filters are configured to filter at different timings and configured using capacitive elements formed in the plurality of successive approximation AD converters, respectively, and
wherein the plurality of successive approximation AD converters are configured to convert output signals of the plurality of discrete time type filters from analog signals to digital signals, respectively.

12. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the first quantizer is a successive approximation type AD converter and is configured to output a voltage of a node, at which a voltage corresponding to the probe signal is held in the first quantizer, as the extraction signal.

13. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the first quantifier is a successive approximation AD converter, and
wherein the first quantifier comprises:
a sample-hold circuit for sampling and holding the output signal of the first analog integrator;
a DA converter configured using the sample-hold circuit and for converting a digital signal successively output from a comparison control unit to an analog signal;
a comparator for comparing a voltage of an output signal of the first analog integrator held by the sample-hold circuit with a voltage of the analog signal converted by the DA converter; and
the comparison control unit for switching a value of the digital signal based on the comparison result by the comparator,
wherein the sample-hold circuit includes a plurality of first capacitive elements arranged in parallel and a second capacitive element arranged in parallel to the plurality of first capacitive elements,
wherein the second capacitive element samples and holds a voltage corresponding to the probe signal, and
wherein the voltage corresponding to the probe signal, which is held in the sample-hold circuit, is output as the extraction signal.

14. The MASH type sigma delta AD converter device according to claim 1 , further comprising:
a first thinning circuit for thinning out a plurality of tap coefficients used to represent the first transfer function searched for by the first adaptive filter in accordance with the operation frequency of the first AD converter; and
a second thinning circuit for thinning out a plurality of tap coefficients used to represent the second transfer function searched for by the second adaptive filter in accordance with the operation frequency of the first AD converter,
wherein the noise cancellation circuit cancels the quantization error and the probe signal included in the output signal of the first quantizer using an output of the first thinning circuit and an output of the second thinning circuit.

15. The MASH type sigma delta AD converter device according to claim 14 , further comprising:
a digital filter for filtering the output signal of the first quantizer,
wherein the first thinning circuit is further configured to multiply the first transfer function by a transfer function of the digital filter, and
wherein the first thinning circuit is configured to thins out a plurality of tap coefficients used to represent a transfer function calculated by multiplying the first transfer function by the transfer function of the digital filter, in accordance with the operation frequency of the first AD converter.

16. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the probe signal is a 1-bit pseudo random signal.

17. The MASH type sigma delta AD converter device according to claim 1 ,
wherein the noise cancellation circuit includes a first noise cancellation filter in which the first transfer function searched for by the first adaptive filter is set as transfer function, a second noise cancellation filter in which the second transfer function searched for by the second adaptive filter is set as transfer function, and a digital adder-subtractor for outputting a differential signal between an output signal of the first noise cancellation filter and a

Assignees

• Renesas Electronics Corp

Inventors

• Oshima Takashi
• Matsui Tetsuo
• Fukazawa Mitsuya
• Tateyama Katsuki
• Fujiwara Masaki

Classifications

• H03M3/386

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• G01S13/931

  of land vehicles · CPC title

• G01S7/354 Primary

  Extracting wanted echo-signals (Doppler systems G01S13/50) · CPC title

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title