Robust current sensing during inverse current load conditions

Patent metadata

Field	Value
Publication number	US-11411562-B2
Application number	US-201916515546-A
Country	US
Kind code	B2
Filing date	Jul 18, 2019
Priority date	Jul 18, 2019
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A current sensing circuit includes load transistors having a current path coupled between a power terminal and corresponding load terminals, sense transistors having a current path coupled between the power terminal and corresponding sense terminals, each sense transistor being coupled to a respective load transistor, N-channel transistors having a current path coupled between a respective sense transistor and a respective sense terminal, an amplifier for selectively equalizing the voltages across one of the load transistors and one of the sense transistors, and bypass circuits coupled to a bulk terminal of the N-channel transistors.

First claim

What is claimed is:

1. A current sensing circuit comprising:
a load transistor having a current path coupled between a power terminal and a load terminal, and a control terminal;
a sense transistor having a current path coupled between the power terminal and a sense terminal, and a control terminal coupled to the control terminal of the load transistor;
a P-channel transistor having a current path coupled between the sense transistor and the sense terminal, and a control terminal;
an N-channel transistor having a current path coupled between the sense transistor and the sense terminal, and a control terminal for receiving a control voltage;
an amplifier for equalizing the voltages across the load transistor and the sense transistor, having an output coupled to the control terminal of the P-channel transistor; and
a bypass circuit directly connected to a bulk terminal of the N-channel transistor, and wherein the bulk terminal of the N-channel transistor is separate from a source terminal of the N-channel transistor.

2. The current sensing circuit of claim 1 , wherein the bypass circuit comprises a local ground connection.

3. The current sensing circuit of claim 1 , wherein the bypass circuit comprises a voltage regulator.

4. The current sensing circuit of claim 1 , wherein the bypass circuit comprises a buffer amplifier coupled between the bulk terminal of the N-channel transistor and the source terminal of the N-channel transistor.

5. The current sensing circuit of claim 4 , wherein the buffer amplifier comprises:
a first N-channel transistor in series with a first current source coupled between the power terminal and a local ground connection;
a P-channel transistor in series with a second current source coupled between the power terminal and the local ground connection; and
a second N-channel transistor coupled to the first N-channel transistor and the P-channel transistor.

6. The current sensing circuit of claim 5 , wherein a gate terminal of the first N-channel transistor comprises an input of the buffer amplifier, and a source terminal of the second N-channel transistor comprises an output of the buffer amplifier.

7. The current sensing circuit of claim 5 , wherein a bulk terminal of the first and second N-channel transistors is coupled to a local ground connection.

8. The current sensing circuit of claim 1 , wherein the bulk terminal of the N-channel transistor is coupled to the source terminal of the N-channel transistor through the bypass circuit.

9. The current sensing circuit of claim 1 , wherein the bypass circuit comprises a buffer coupled between the power terminal and a local ground connection.

10. The current sensing circuit of claim 1 , further comprising an integrated substrate including a P-type guard structure proximate to the sense transistor and the load transistor.

11. The current sensing circuit of claim 1 , further comprising an additional P-channel transistor having a current path coupled between the sense transistor and the sense terminal.

12. A current sensing circuit comprising:
a plurality of load transistors having a current path coupled between a power terminal and a plurality of load terminals;
a plurality of sense transistors having a current path coupled between the power terminal and a sense terminal, each sense transistor being coupled to a respective load transistor;
a plurality of N-channel transistors having a current path coupled between a respective sense transistor and a respective sense terminal;
an amplifier for selectively equalizing the voltages across one of the load transistors and one of the sense transistors; and
a plurality of bypass circuits coupled to a bulk terminal of the plurality of N-channel transistors.

13. The current sensing circuit of claim 12 , wherein each of the plurality of bypass circuits comprises a local ground connection.

14. The current sensing circuit of claim 12 , wherein each of the plurality of bypass circuits comprises a voltage regulator.

15. The current sensing circuit of claim 12 , wherein each of the bypass circuits comprises a buffer amplifier coupled between the bulk terminal of a respective N-channel transistor and a source terminal of the respective N-channel transistor.

16. The current sensing circuit of claim 12 , wherein each of the bypass circuits is further coupled to a local ground connection.

17. A current sensing method, the method comprising:
providing a load current in a first current path;
sensing the load current to provide a sense current in a second current path;
passing the sense current through an N-channel transistor in the second current path; and
bypassing a parasitic current flowing out of a bulk terminal of the N-channel transistor so that it is not added to the sense current in the second current path, wherein the parasitic current is bypassed through a bypass circuit directly coupled to the bulk terminal, and wherein the bulk terminal of the N-channel transistor is separate from a source terminal of the N-channel transistor.

18. The current sensing method of claim 17 , wherein bypassing the parasitic current comprises shunting the parasitic current to a local ground connection of the bypass circuit.

19. The current sensing method of claim 17 , wherein bypassing the parasitic current comprises shunting the parasitic current to a voltage regulator of the bypass circuit.

20. The current sensing method of claim 17 , wherein bypassing the parasitic current comprises shunting the parasitic current to an output of a buffer amplifier of the bypass circuit, wherein the buffer amplifier is coupled to the source terminal of the N-channel transistor.

21. The current sensing method of claim 20 , wherein the buffer amplifier is further coupled to a local ground connection.

Assignees

• Infineon Technologies Ag

Inventors

• Tranca Ioan-Alexandru
• Brugger Florian
• Mayer Alexander

Classifications

• H10D84/141

  VDMOS having built-in components · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• G01R19/0046 Primary

  characterised by a specific application or detail not covered by any other subgroup of G01R19/00 · CPC title

• G01R19/0092

  Measuring current only · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title