Method and apparatus for controlling modes of inverter circuit, and inverter

Patent metadata

Field	Value
Publication number	US-11411488-B2
Application number	US-202016932273-A
Country	US
Kind code	B2
Filing date	Jul 17, 2020
Priority date	Aug 6, 2019
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A method and apparatus for controlling a neutral point clamped inverter circuit, and a neutral point clamped inverter. It is detected that whether the inverter circuit operates in an abnormal state. In a case that the inverter circuit operates in the abnormal state, a control mode of the inverter circuit is changed to a specified control mode in which a transistor that may be damaged is in an off state. In this way, there is not current flowing through the transistor, avoiding damage of the transistor and thereby improving safety of the inverter circuit.

First claim

The invention claimed is:

1. A method for controlling an inverter circuit, wherein the inverter circuit has at least two control modes, and the inverter circuit is able to operate in a normal state under each of the at least two control modes; the method comprising:
detecting whether the inverter circuit operates in an abnormal state, wherein the abnormal state comprises a state when a power factor of the inverter circuit is less than a preset value; and
changing a control mode of the inverter circuit from an original control mode to a specified control mode in response to detecting that the inverter circuit operates in the abnormal state, wherein the specified control mode is one of the at least two control modes of the inverter circuit, a specified transistor is in a low frequency state under the specified control mode, and the specified transistor is a transistor whose current flowing through the specified transistor is greater than a maximum allowable collector current of the specified transistor when the inverter circuit operates in the abnormal state.

2. The method according to claim 1 , further comprising:
changing the control mode of the inverter circuit from the specified control mode to the original control mode, in response to detecting that the inverter circuit recovers to the normal state from the abnormal state.

3. The method according to claim 1 , wherein the inverter circuit is a neutral point clamped three-level inverter circuit, the inverter circuit comprising:
a first capacitor and a second capacitor connected in series, wherein a first terminal of the first capacitor is connected to a first terminal of the second capacitor, and a second terminal of the first capacitor is connected to a positive pole of a direct current power supply, and a second terminal of the second capacitor is connected to a negative pole of the direct current power supply;
a first transistor, a fifth transistor, a sixth transistor and a fourth transistor sequentially connected in series, to form a first series branch, wherein a first terminal of the first series branch is connected to the second terminal of the first capacitor, and a second terminal of the first series branch is connected to the second terminal of the second capacitor; and
a second transistor and a third transistor connected in series, to form a second series branch, wherein a first terminal of the second series branch is connected to a connection node between the fifth transistor and the first transistor, a second terminal of the second series branch is connected to a connection node between the sixth transistor and the fourth transistor, and a connection node between the second transistor and the third transistor is an output terminal of the inverter circuit.

4. The method according to claim 3 , wherein the at least two control modes comprise a first control mode, a second control mode and a third control mode, wherein
during a positive half period under the first control mode, a control signal of the first transistor and a control signal of the fifth transistor are in a high frequency chopping state, a control signal of the second transistor, a control signal of the third transistor, a control signal of the fourth transistor and a control signal of the sixth transistor are in a low frequency state; during a negative half period under the first control mode, the control signal of the fourth transistor and the control signal of the sixth transistor are in the high frequency chopping state, the control signal of the first transistor, the control signal of the fifth transistor, the control signal of the second transistor and the control signal of the third transistor are in the low frequency state;
during a full period under the second control mode, the control signal of the second transistor and the control signal of the third transistor are in the high frequency chopping state, the control signal of the first transistor, the control signal of the fourth transistor, the control signal of the fifth transistor and the control signal of the sixth transistor are in the low frequency state;
during a positive half period under the third control mode, the control signal of the first transistor and the control signal of the third transistor are in the high frequency chopping state, the control signal of the second transistor and the control signal of the fourth transistor are in the low frequency state; and during a negative half period under the third control mode, the control signal of the second transistor and the control signal of the fourth transistor are in the high frequency chopping state, and the control signal of the first transistor and the control signal of the third transistor are in the low frequency state.

5. The method according to claim 4 , wherein
the specified control mode is the third control mode or the second control mode, in a case that the original control mode is the first control mode;
alternatively, the specified control mode is the first control mode, in a case that the original control mode is the second control mode or the third control mode.

6. An apparatus for controlling an inverter circuit, wherein the inverter circuit has at least two control modes, and the inverter circuit is able to operate in a normal state under each of the at least two control modes; the apparatus comprising:
a detection module, configured to detect whether the inverter circuit operates in an abnormal state, wherein the abnormal state comprises a state when a power factor of the inverter circuit is less than a preset value; and
a control module, configured to control an operation state of the inverter circuit, and change a control mode of the inverter circuit to a specified control mode in a case that the inverter circuit operates in the abnormal state, wherein the specified control mode is one of the at least two control modes of the inverter circuit, a specified transistor is in a low frequency state under the specified control mode, and the specified transistor is a transistor whose current flowing through the specified transistor is greater than a maximum allowable collector current of the specified transistor when the inverter circuit operates in the abnormal state.

7. An inverter, comprising:
an inverter circuit, wherein the inverter circuit has at least two control modes, and the inverter circuit is able to operate in a normal state under each of the at least two control modes; and
a controller, configured to control the inverter circuit, detect whether the inverter circuit operates in an abnormal state, and change a control mode of the inverter circuit from an original control mode to a specified control mode in a case that the inverter circuit operates in the abnormal state,
wherein the abnormal state comprises a state when a power factor of the inverter circuit is less than a preset value, and the specified control mode is one of the at least two control modes of the inverter circuit, a specified transistor is in a low frequency state under the specified control mode, and the specified transistor is a transistor whose current flowing through the specified transistor is greater than a maximum allowable collector current of the specified transistor when the inverter circuit operates in the abnormal state.

8. The inverter according to claim 7 , wherein the inverter circuit is a neutral point clamped three-level inverter circuit, the inverter circuit comprising:
a first capacitor and a second capacitor connected in series, wherein a first terminal of the first capacitor is connected to a first terminal of the second capacitor, a second terminal of the first capacitor is connected to a positive pole of a direct current power supply, and a second terminal of the second capacitor is connected t

Assignees

• Sungrow Power Supply Co Ltd

Inventors

• Chen Peng
• Cao Jinhu
• Bie Wei
• Lin Leiming

Classifications

• H02M1/42

  Circuits or arrangements for compensating for or adjusting power factor in converters or inverters · CPC title

• H02M7/539

  with automatic control of output wave form or frequency (H02M7/5375 - H02M7/5387 take precedence) · CPC title

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/325

  with means for allowing continuous operation despite a fault, i.e. fault tolerant converters · CPC title

• H02M7/487 Primary

  Neutral point clamped inverters · CPC title