Quantum spin hall-based charging energy-protected quantum computation
US-2019220769-A1 · Jul 18, 2019 · US
Silicon-based Josephson junction for qubit devices
US11411160B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11411160-B2 |
| Application number | US-202016748277-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 21, 2020 |
| Priority date | Jan 21, 2020 |
| Publication date | Aug 9, 2022 |
| Grant date | Aug 9, 2022 |
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Abstract
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Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes.
First claim
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What is claimed is: 1. An apparatus, comprising: a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes, wherein the two vertically stacked superconducting electrodes comprise a first superconducting electrode and a second superconducting electrode, and wherein the first superconducting silicon electrode and the second superconducting silicon electrode each comprise a laser doped crystalline silicon material doped with boron, wherein a concentration of the boron in each of the first superconducting electrode and the second superconducting electrode is greater than or equal to 4 atomic percent boron and less than or equal to 11 atomic percent boron; and isolation layer positioned on the tunnel barrier and connected to a first side of the first superconducting electrode and a second side of the first superconducting electrode such that the isolation layer electrically isolates the first side of the first superconducting electrode and the second side of the first superconducting electrode, the first side being opposite the second side. 2. The apparatus of claim 1 , wherein the two vertically stacked superconducting silicon electrodes also comprise silicon doped with at least one other dopant selected from the group consisting of gallium, and germanium. 3. The apparatus of claim 1 , further comprising: a first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; and a second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, wherein the isolation layer positioned on the tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer comprises a carbon implantation within silicon. 4. The apparatus of claim 1 , further comprising: a first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; and a second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, wherein the isolation layer positioned on the tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer comprises intrinsic silicon. 5. The apparatus of claim 1 , wherein the tunnel barrier is doped with at least one dopant selected from the group consisting of phosphorus and arsenic. 6. The apparatus of claim 1 , wherein the tunnel barrier comprises intrinsic crystalline silicon. 7. An apparatus, comprising: a Josephson junction comprising a dielectric tunnel barrier positioned between two superconducting silicon electrodes, wherein the superconducting silicon electrodes comprise a first superconducting electrode and a second superconducting electrode, and wherein at least one of the first superconducting silicon electrode or the second superconducting silicon electrode comprises a laser doped crystalline silicon material doped with boron, wherein a concentration of the boron in the first superconducting electrode or the second superconducting electrode is greater than or equal to 4 atomic percent boron and less than or equal to 11 atomic percent boron; and isolation layer positioned on the dielectric tunnel barrier and connected to a first side of the first superconducting electrode and a second side of the first superconducting electrode such that the isolation layer electrically isolates the first side of the first superconducting electrode and the second side of the first superconducting electrode, the first side being opposite the second side. 8. The apparatus of claim 7 , wherein the two superconducting silicon electrodes comprise silicon doped with at least one other dopant selected from the group consisting of germanium, and gallium. 9. The apparatus of claim 7 , further comprising: a first metal contact operably coupled to a first superconducting silicon electrode from the two superconducting silicon electrodes; and a second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes, wherein the isolation layer is positioned on the dielectric tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer comprises a carbon implantation within silicon. 10. The apparatus of claim 7 , further comprising: a first metal contact operably coupled to a first superconducting silicon electrode from the two superconducting silicon electrodes; and a second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes, and wherein the isolation layer positioned on the dielectric tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer comprises intrinsic silicon. 11. The apparatus of claim 7 , wherein the dielectric tunnel barrier comprises intrinsic crystalline silicon. 12. The apparatus of claim 7 , wherein the two superconducting silicon electrodes and the dielectric tunnel barrier are vertically stacked on a dielectric substrate.
Assignees
Inventors
Classifications
Electricity · mapped topic
- H01L39/2487Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
comprising metal borides, e.g. MgB2 · CPC title
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Frequently asked questions
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- What does patent US11411160B2 cover?
- Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon elec…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H01L39/2487. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 09 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).