Syndrome data compression for quantum computing devices

Patent metadata

Field	Value
Publication number	US-11410070-B2
Application number	US-201916687517-A
Country	US
Kind code	B2
Filing date	Nov 18, 2019
Priority date	Aug 6, 2019
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

First claim

The invention claimed is:

1. A quantum computing device, comprising:
at least one quantum register including a plurality of logical qubits;
a compression engine coupled to each logical qubit of the plurality of logical qubits, each compression engine configured to compress syndrome data; and
a decompression engine coupled to each compression engine, each decompression engine configured to:
receive compressed syndrome data;
decompress the received compressed syndrome data; and
route the decompressed syndrome data to a decoder block.

2. The quantum computing device of claim 1 , wherein at least one of the compression engines are configured to compress the syndrome data using dynamic zero compression.

3. The quantum computing device of claim 1 , wherein at least one of the compression engines are configured to compress the syndrome data using sparse representation.

4. The quantum computing device of claim 1 , wherein at least one of the compression engines are configured to compress the syndrome data using geometry-based compression.

5. The quantum computing device of claim 1 , wherein the plurality of logical qubits are divided into two or more sectors, and wherein a first sector of the one or more sectors is coupled to a first type of compression engine configured to compress syndrome data using a first type of compression, and a second sector of the one or more sectors is coupled to a second type of compression engine configured to compress syndrome data using a second type of compression.

6. The quantum computing device of claim 1 , wherein the compression engine is configured to operate at a higher temperature than the quantum register.

7. The quantum computing device of claim 6 , wherein the decompression engine and decoder blocks are configured to operate at a higher temperature than the compression engine.

8. The quantum computing device of claim 1 , wherein each decompression engine routes decompressed syndrome data to a Graph-Generator module of the decoder block.

9. The quantum computing device of claim 1 , wherein the decompressed syndrome data includes at least X syndrome data and Z syndrome data.

10. The quantum computing device of claim 1 , wherein the plurality of logical qubits includes l logical qubits, and wherein the quantum computing device comprises a set of d decoder blocks, where d<l.

11. A method for a quantum computing device, comprising:
generating syndrome data from at least one quantum register including l logical qubits, where l is a positive integer; and
for each logical qubit:
routing the generated syndrome data to a compression engine, the compression engine configured to compress syndrome data;
routing the compressed syndrome data to a decompression engine, the decompression engine configured to:
receive compressed syndrome data; and
decompress the received compressed syndrome data; and

routing the decompressed syndrome data to a decoder block.

12. The method of claim 11 , wherein at least one of the compression engines is configured to compress the syndrome data using dynamic zero compression.

13. The method of claim 11 , wherein at least one of the compression engines is configured to compress the syndrome data using sparse representation.

14. The method of claim 11 , further comprising operating the compression engine at a higher temperature than the quantum register.

15. The method of claim 14 , further comprising operating the decompression engine and decoder blocks at a higher temperature than the compression engine.

16. The method of claim 11 , wherein each decompression engine routes decompressed syndrome data to a Graph-Generator module of the decoder block.

17. The method of claim 11 , wherein the quantum computing device comprises a set of d decoder blocks, where d<2*l.

18. A method for a quantum computing device, comprising:
generating syndrome data from at least one surface code lattice including l logical qubits, where l is a positive integer, the surface code lattice partitioned into two or more regions based on lattice geometry; and
for each logical qubit:
routing the generated syndrome data to a compression engine, the compression engine configured to compress syndrome data using geometry-based compression;
routing the compressed syndrome data to a decompression engine, the decompression engine configured to:
receive compressed syndrome data; and
decompress the received compressed syndrome data; and

routing the decompressed syndrome data to a decoder block.

19. The method of claim 18 , wherein compressing syndrome data using geometry-based compression includes:
compressing syndrome data using a zero indicator bit for each region of the two or more regions of the surface code lattice; and
transmitting syndrome data only from non-zero regions.

20. The method of claim 18 , wherein the number of regions is determined based on an expected number of data blocks that contain trivial syndromes.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Das Poulami
• Delfosse Nicolas Guillaume
• Pattison Christopher Anand
• Manne Srilatha
• Carmean Douglas
• Svore Krysta Marie
• Katzgraber Helmut Gottfried

Classifications

• G06F18/2323

  based on graph theory, e.g. minimum spanning trees [MST] or graph cuts · CPC title

• G06N5/01

  Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06F9/3869

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title