Communication systems with serial peripheral interface functionality

Patent metadata

Field	Value
Publication number	US-11409690-B2
Application number	US-202017110126-A
Country	US
Kind code	B2
Filing date	Dec 2, 2020
Priority date	May 8, 2019
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

First claim

The invention claimed is:

1. An apparatus with serial peripheral interface (SPI) functionality, comprising: a first node transceiver, wherein the first node transceiver includes transceiver circuitry to receive a signal transmitted over two wires of a two-wire bus from a second node transceiver; wherein the first node transceiver includes Inter-Integrated Circuit (I2C) circuitry to allow the first node transceiver to interface with an I2C slave, the second node transceiver includes SPI circuitry to allow the second node transceiver to interface with an SPI host, and the I2C slave is to respond to commands transmitted from the SPI host and over the two-wire bus.

2. The apparatus of claim 1 , wherein:
the SPI circuitry is further to receive a first SPI command from the SPI host and, in response to receipt of the first SPI command, transmit a first I2C command to the first node transceiver over the two wires; and
in response to receipt of the first I2C command, the first node transceiver is to transmit a second I2C command to the I2C slave.

3. The apparatus of claim 2 , wherein the first SPI command includes an I2C read request command, the first I2C command includes an I2C read command, and the second I2C command includes an I2C read command.

4. The apparatus of claim 3 , wherein the SPI circuitry is to receive, from the first node transceiver via the transceiver circuitry, read data in response to the read command transmitted to the first node transceiver.

5. The apparatus of claim 4 , wherein the read data is provided to the I2C circuitry of the first node transceiver by the I2C slave.

6. The apparatus of claim 4 , wherein the SPI circuitry is to receive, from the SPI host, a first-in-first-out (FIFO) read command, and in response to receipt of the FIFO read command, provide the read data to the SPI host.

7. The apparatus of claim 2 , wherein the first SPI command includes an I2C write command, the first I2C command includes a write command, and the second I2C command includes a write command.

8. The apparatus of claim 2 , wherein the first SPI command includes an indicator of the first node transceiver and an indicator of the I2C slave.

9. The apparatus of claim 1 , wherein the SPI circuitry includes a slave select port, a bit clock port, a master-out-slave-in port, and a master-in-slave-out port, wherein the I2C circuitry includes a data port and a clock port.

10. The apparatus of claim 1 , wherein the transceiver circuitry is first transceiver circuitry, the two wires are a first two wires, the first node transceiver further includes second transceiver circuitry to receive a signal transmitted over a second two wires of the two-wire bus from a third node transceiver, and (a) the first transceiver circuitry is upstream transceiver circuitry and the second transceiver circuitry is downstream transceiver circuitry, or (b) the first transceiver circuitry is downstream transceiver circuitry and the second transceiver circuitry is upstream transceiver circuitry.

11. The apparatus of claim 10 , wherein the first node transceiver further includes: clock circuitry to generate a clock signal at the first node transceiver based on a preamble of a synchronization control frame in a first signal received via two upstream wires of the two-wire bus, wherein timing of the receipt and provision of signals over the two-wire bus by the first node transceiver is based on the clock signal; and
power circuitry to receive a voltage bias over between the two upstream wires of the two-wire bus from the third node transceiver.

12. The apparatus of claim 1 , wherein the first node transceiver is a slave node transceiver.

13. The apparatus of claim 1 , further comprising: the SPI host.

14. The apparatus of claim 1 , further comprising: the second node transceiver.

15. The apparatus of claim 1 , further comprising: the I2C slave.

16. The apparatus of claim 1 , wherein the two-wire bus includes an unshielded twisted pair.

17. The apparatus of claim 1 , wherein the apparatus is at least partially included in a vehicle.

18. A method of providing serial peripheral interface (SPI) functionality for a node in a communication system, comprising:
transmitting a signal from a second node transceiver over two wires of a two-wire bus, wherein the second node transceiver includes SPI circuitry to allow the second node transceiver to interface with an SPI host;
receiving the signal at transceiver circuitry in a first node, wherein the first node transceiver includes Inter-Integrated Circuit (I2C) circuitry to allow the first node transceiver to interface with an I2C slave;
responding, from the I2C slave, to commands transmitted from the SPI host over the two-wire bus.

19. The method of claim 18 , further comprising:
receiving, at the SPI circuitry, a first SPI command from the SPI host;
transmitting, from the SPI circuitry in response to receipt of the first SPI command, a first I2C command to the first node transceiver over the two wires; and
transmitting, from the first node transceiver, a second I2C command to the I2C slave in response to receipt of the first I2C command.

20. A communication system for providing serial peripheral interface SPI functionality, comprising
an SPI host;
an I2C slave;
a first node transceiver, wherein the first node transceiver includes transceiver circuitry and Inter-Integrated Circuit (I2C) circuitry to allow the first node transceiver to interface with the I2C slave;
a second node transceiver, wherein the second node transceiver includes SPI circuitry to allow the second node transceiver to interface with the SPI host;
wherein the first node transceiver is to receive a signal transmitted over two wires of a two wire bus from the second node transceiver, and
wherein the I2C slave is to respond to commands transmitted from the SPI host and over the two-wire bus.

Assignees

• Analog Devices Inc

Inventors

• Kessler Martin
• Lahr Lewis F
• Hooper William

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G06F2213/0016

  Inter-integrated circuit (I2C) · CPC title

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title