Hardware bit-vector techniques

Patent metadata

Field	Value
Publication number	US-11409617-B2
Application number	US-202016882402-A
Country	US
Kind code	B2
Filing date	May 22, 2020
Priority date	May 22, 2020
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.

First claim

What is claimed is:

1. A device, comprising:
energy harvesting circuitry that experiences power failures; and
computing circuitry having a processor coupled to the energy harvesting circuitry, wherein the processor is configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.

2. The device of claim 1 , wherein the device refers to a battery-less energy harvesting sensor that operates intermittently when energy is available for harvesting and for producing power for load circuitry including the processor.

3. The device of claim 1 , further comprising:
non-volatile memory (NVM) that is used as persistent memory to provide a checkpoint for one or more program states so that the one or more program states are restored when power is available during energy harvesting.

4. The device of claim 3 , wherein the log structure is used to ensure that the checkpoint remains consistent with respect to the one or more program states, and wherein the log structure is used to ensure that the number of write operations are restorable by writing to the hardware bit-vector.

5. The device of claim 3 , wherein the hardware bit-vector is used so as to enable undo-logging, wherein the number of write operations has a first write operation, and wherein the undo-logging is only used on the first write operation after a checkpoint, and wherein the first write operation is write-specific to at least one variable associated with the first write operation.

6. The device of claim 3 , wherein the hardware bit-vector is configured to track the one or more program states between multiple checkpoints.

7. The device of claim 1 , wherein the hardware bit-vector refers to a compiler mapped, status flag bits or register for software log filtering of one or more program states during execution of the number of write operations.

8. The device of claim 1 , further comprising power conversion circuitry that is coupled to the energy harvesting circuitry and the computing circuitry,
wherein the power conversion circuitry is configured to convert energy harvested by the energy harvesting circuitry to power for use by the computing circuitry.

9. The device of claim 1 , wherein the processor is configured to:
execute a test-and-log function that reads the hardware bit-vector and updates an undo log if the hardware bit-vector is not set, wherein the test-and-log function obtains an address of each variable to be logged and a corresponding index into the hardware bit-vector, and wherein the test-and-log function refers to a single instruction or an instruction sequence provided by instruction set architecture (ISA).

10. A method, comprising:
tracking a program state for a number of write operations with checkpoints;
for each checkpoint, identifying variables to be stored in persistent memory that are written before a next checkpoint;
assigning a bit in a hardware bit-vector for each variable of the variables to be stored in the persistent memory; and
verifying the variables to be stored in the persistent memory.

11. The method of claim 10 , wherein assigning the bit in the hardware bit-vector for each variable of the variables refers to mapping each variable of the variables to the bits in the hardware bit-vector.

12. The method of claim 10 , wherein the persistent memory comprises non-volatile memory (NVM) that is used to provide the checkpoints for each program state.

13. The method of claim 10 , wherein assigning the bit in the hardware bit-vector for each variable of the variables refers to using the hardware bit-vector to filter the number of write operations with respect to a log structure stored in the persistent memory.

14. The method of claim 13 , wherein the log structure is used to ensure that the persistent memory remains consistent with respect to each program state, and wherein the log structure is used to ensure that the number of write operations are restored by writing to the persistent memory with the hardware bit-vector.

15. The method of claim 10 , wherein the hardware bit-vector is used so as to enable undo-logging, wherein the number of write operations includes a first write operation, and wherein the undo-logging is only used on the first write operation after encountering a checkpoint.

16. The method of claim 10 , wherein the hardware bit-vector refers to a compiler mapped, status flag register for software log filtering of each program state during execution of the number of write operations.

17. A system, comprising:
a processor; and
memory having instructions stored thereon that, when executed by the processor, cause the processor to:
identify a hardware bit-vector comprising a plurality of bits, each bit assigned to a variable stored in the memory;
identify an undo log stored in the memory; and
execute a test-and-log instruction that reads a bit of the hardware bit-vector and update the undo log in dependence on a value of the bit of the hardware bit-vector.

18. The system of claim 17 , wherein the instructions cause the processor to:
if the hardware bit-vector is not set, then the test-and-log instruction updates the undo log and obtains an address of each variable to be logged and a corresponding index into the hardware bit-vector.

19. The system of claim 17 , wherein:
the system refers to a battery-less energy harvesting sensor that operates intermittently when energy is available for harvesting and for producing power for the processor and the memory, and
the memory comprises non-volatile memory (NVM) that is used as persistent memory to provide each checkpoint for the program states so that the program states are restored when power is available during energy harvesting.

20. The system of claim 17 , further comprising:
energy harvesting circuitry that experiences frequent power failures, wherein:
the processor and memory are coupled to the energy harvesting circuitry, and
the processor is configured to reduce the number of write operations to a log structure with the hardware bit-vector that is used by the energy-harvesting circuitry to compensate for the frequent power failures.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Ruppel Emily Kathryn
• Jeloka Supreet
• Savanth Parameshwarappa Anand Kumar
• Wang Wei

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F2201/84

  Using snapshots, i.e. a logical point-in-time copy of the data · CPC title

• G06F11/2051

  in regular structures · CPC title

• H02J50/001

  Energy harvesting or scavenging · CPC title

• G06F11/1471 Primary

  involving logging of persistent data for recovery · CPC title