Bonding pad layer system, gas sensor and method for manufacturing a gas sensor

Patent metadata

Field	Value
Publication number	US-11407635-B2
Application number	US-201816625185-A
Country	US
Kind code	B2
Filing date	Jun 14, 2018
Priority date	Jun 23, 2017
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A bonding pad layer system is deposited on a semiconductor chip as a base, for example, a micromechanical semiconductor chip, in which at least one self-supporting dielectric membrane made up of dielectric layers, a platinum conductor track and a heater made of platinum is integrated. In the process, the deposition of a tantalum layer takes place first, upon that the deposition of a first platinum layer, upon that the deposition of a tantalum nitride layer, upon that the deposition of a second platinum layer and upon that the deposition of a gold layer, at least one bonding pad for connecting with a bonding wire being formed in the gold layer. The bonding pad is situated in the area of the contact hole on the semiconductor chip, in which a platinum conductor track leading to the heater is connected using a ring contact and/or is connected outside this area.

First claim

What is claimed is:

1. A bonding pad layer system, comprising:
a semiconductor chip as a base, upon which a tantalum layer, a first platinum layer, a tantalum nitride layer, a second platinum layer, and a gold layer, are sequentially deposited, at least one bonding pad being formed in the gold layer for connecting to a bonding wire.

2. The bonding pad layer system as recited in claim 1 , wherein the semiconductor chip is a micromechanical semiconductor chip, in which at least one self-supporting dielectric membrane including dielectric layers, a platinum conductor track and a heater made of platinum is integrated.

3. The bonding pad layer system as recited in claim 2 , wherein at least one of the at least one bonding pad is situated in an area of a contact hole on the semiconductor chip, in which a platinum conductor track leading to the heater is electrically connected with using a ring contact.

4. The bonding pad layer system as recited in claim 1 , wherein at least one of the at least one bonding pad is situated in an area outside the contact hole on the semiconductor chip.

5. A bonding pad layer system as recited in claim 1 , wherein:
a layer thickness of the tantalum layer is 2 to 200 nanometers,
a layer thickness of the first platinum layer is 50 to 1000 nanometers,
a layer thickness of the tantalum nitride layer is 2 to 200 nanometers,
a layer thickness of the second platinum layer is 2 to 400 nanometers, and
a layer thickness of the gold layer is 50 to 1000 nanometers.

6. The bonding pad layer system as recited in claim 1 , wherein
a layer thickness of the tantalum layer is 5 to 50 nanometers,
a layer thickness of the first platinum layer is 100 to 500 nanometers,
a layer thickness of the tantalum nitride layer is 5 to 50 nanometers,
a layer thickness of the second platinum layer is 10 to 150 nanometers, and
a layer thickness of the gold layer is 200 to 600 nanometers.

7. The bonding pad layer system as recited in claim 1 , wherein a layer composition of the tantalum nitride layer is made up of tantalum (Ta) and nitrogen (N) in the ratio Ta x N y , x being between 1 and 5 and y being capable of varying between 0.04 and 6.

8. The bonding pad layer system as recited in claim 1 , wherein a layer composition of the tantalum nitride layer is stoichiometric.

9. The bonding pad layer system as recited in claim 1 , wherein the tantalum layer and the first platinum layer are electrical electrodes and conducting tracks).

10. The boding pad layer system as recited in claim 2 , wherein the micromechanical semiconductor chip is a gas sensor.

11. A method for manufacturing a gas sensor including a bonding pad layer system and a paste dot, comprising the following steps in the order:
a) providing a micromechanical semiconductor chip as a base, in which at least one self-supporting dielectric membrane made up of dielectric layers and a platinum conductor track for electrically contacting a heater made of platinum is integrated;
b) depositing a tantalum layer;
c) depositing a first platinum layer;
d) depositing a tantalum nitride layer;
e) depositing a second platinum layer;
f) depositing a gold layer;
g) providing at least one bonding pad for connecting to a bonding wire on the gold layer in an area of a contact hole on the semiconductor chip, in which a platinum conductor track leading to the heater is connected using a ring contact, and providing at least one bonding pad outside a contact hole, which is used to electrically contact electrode structures and conductor tracks;
h) providing the electrode structures and the conductor tracks;
i) providing a paste dot; and
j) sintering the paste dot.

12. The method as recited in claim 11 , wherein the tantalum nitride layer is formed by tempering tantalum layers at temperatures above 600° C. in an ammonia/hydrogen atmosphere or in a nitrogen/hydrogen atmosphere.

13. The method as recited in claim 11 , wherein the tantalum layer and the first platinum layer are etched to form the electrode structures and conductor tracks, the etching capable of taking place using IBE etching and/or plasma etching and/or wet chemical etching.

Assignees

• Bosch Gmbh Robert

Inventors

• Scheurle Andreas
• Klein Bernd
• Nedelmann Heinz
• Weber Heribert
• Simon Isolde
• Lapisa Martin
• Delheusy Melissa
• Knauss Michael
• Baraki Raschid
• Kondrashov Vitaliy

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/01961

  Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951) · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title