Decoding method and decoding apparatus

Patent metadata

Field	Value
Publication number	US-11405135-B2
Application number	US-202117316817-A
Country	US
Kind code	B2
Filing date	May 11, 2021
Priority date	Nov 12, 2018
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A decoding method performed by a receive end device is disclosed. The decoding method includes: receiving a first bit signal; performing level-M forward error correction (FEC) decoding on the first bit signal to obtain a second bit signal, where M is a positive integer greater than zero; checking the second bit signal to obtain a first check result; performing level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal; and, upon determining that M+1 reaches a first preset threshold, performing data processing on the third bit signal to obtain a fourth bit signal, where the fourth bit signal is used by the receive end device to obtain service data transmitted by a transmit end device.

First claim

What is claimed is:

1. A decoding method, comprising:
receiving, by a receive end device, a first bit signal;
performing, by the receive end device, level-M forward error correction (FEC) decoding on the first bit signal to obtain a second bit signal, wherein M is a positive integer greater than zero;
checking, by the receive end device, the second bit signal to obtain a first check result;
performing, by the receive end device, level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal; and
upon determination that M+1 reaches a first threshold, performing, by the receive end device, data processing on the third bit signal to obtain a fourth bit signal, wherein the receive end device uses the fourth bit signal to obtain service data transmitted by a transmit end device,
wherein the checking, by the receive end device, the second bit signal to obtain a first check result comprises:
based upon determining whether a current count of each type of symbol in symbols corresponding to the second bit signal is equal to a preset count of that type of symbol, determining, by the receive end device, the first check result, wherein the first check result indicates whether the checking of the second bit signal is successful, and the current count of each type of symbol is a count of occurrences of the type of symbol in the symbols corresponding to the second bit signal.

2. The method according to claim 1 , wherein the checking, by the receive end device, the second bit signal to obtain a first check result comprises:
upon determination that the current count of each type of symbol in the symbols corresponding to the second bit signal is equal to the preset count of that type of symbol, determining, by the receive end device, the first check result, wherein the first check result indicates that the checking of the second bit signal is successful, and the preset count of each type of symbol is a preset count of occurrences of the type of symbol in symbols corresponding to the first bit signal, and
the performing, by the receive end device, level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal comprises:
adjusting, by the receive end device, a log-likelihood ratio (LLR) value currently corresponding to the second bit signal to obtain a first LLR value, wherein an absolute value of the first LLR value is greater than an absolute value of the LLR value currently corresponding to the second bit signal; and
performing, by the receive end device, level-(M+1) FEC decoding on the second bit signal based on the first LLR value to obtain the third bit signal.

3. The method according to claim 2 , wherein the absolute value of the first LLR value is an absolute value of a preset maximum LLR value corresponding to the second bit signal or K times the absolute value of the LLR value currently corresponding to the second bit signal, wherein K is an integer greater than 1.

4. The method according to claim 1 , wherein the checking, by the receive end device, the second bit signal to obtain a first check result comprises:
upon determination that the current count of each type of symbol in the symbols corresponding to the second bit signal is not equal to the preset count of that type of symbol, determining, by the receive end device, the first check result, wherein the first check result indicates that the checking of the second bit signal fails, and the preset count of each type of symbol is a preset count of occurrences of the type of symbol in symbols corresponding to the first bit signal, and
the performing, by the receive end device, level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal comprises:
adjusting, by the receive end device, a log-likelihood ratio (LLR) value currently corresponding to the second bit signal to obtain a second LLR value, wherein an absolute value of the second LLR value is less than an absolute value of the LLR value currently corresponding to the second bit signal; and
performing, by the receive end device, level-(M+1) FEC decoding on the second bit signal based on the second LLR value to obtain the third bit signal.

5. The method according to claim 2 , further comprising: after performing the level-M FEC decoding on the first bit signal to obtain the second bit signal, and before checking the second bit signal to obtain the first check result,
determining, by the receive end device, the symbols corresponding to the second bit signal.

6. The method according to claim 5 , wherein the determining, by the receive end device, the symbols corresponding to the second bit signal comprises:
performing, by the receive end device, binary labeling (BL) demapping processing on the second bit signal to obtain the symbols corresponding to the second bit signal.

7. The method according to claim 1 , further comprising: after performing the level-M FEC decoding on the first bit signal to obtain the second bit signal, and before checking the second bit signal to obtain the first check result,
determining, by the receive end device, whether the LLR value currently corresponding to the second bit signal is greater than a second threshold; and
upon determination that the LLR value currently corresponding to the second bit signal is greater than the second threshold, triggering the checking of the second bit signal to obtain the first check result.

8. The method according to claim 1 , further comprising:
upon determination that M+1 does not reach the first threshold, checking, by the receive end device, the third bit signal to obtain a second check result, and performing, by the receive end device, level-(M+2) FEC decoding on the third bit signal based on the obtained second check result to obtain a fifth bit signal.

9. The method according to claim 1 , wherein the performing, by the receive end device, data processing on the third bit signal to obtain a fourth bit signal comprises:
performing, by the receive end device, binary labeling (BL) demapping processing on the third bit signal to obtain symbols corresponding to the third bit signal; and
performing, by the receive end device, distribution matching (DM) decoding on the symbols corresponding to the third bit signal to obtain the fourth bit signal, and the method further comprises:
after performing the distribution matching (DM) decoding on the symbols corresponding to the third bit signal to obtain the fourth bit signal,
outputting, by the receive end device, the fourth bit signal.

10. A decoding apparatus, comprising:
a transceiver, configured to receive a first bit signal; and
at least one processor, configured to:
perform level-M forward error correction (FEC) decoding on the first bit signal to obtain a second bit signal, wherein M is a positive integer greater than zero;
check the second bit signal to obtain a first check result;
perform level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal; and upon determination that M+1 reaches a first threshold, perform data processing on the third bit signal to obtain a fourth bit signal, wherein the fourth bit signal is used by a receive end device to obtain service data transmitted by a transmit end device,
wherein the checking of the second bit signal to obtain the first check result comprises:
based upon determining whether a current count of each type of symbol in symbols corresponding to the second bit signal is equal to a preset count of that type of symbol, determining the first check result, wherein the first check result indicates whether the checking of the second bit signal is

Assignees

• Huawei Tech Co Ltd

Inventors

• Huang Yuanda
• Xia Bin

Classifications

• H03M13/63

  Joint error correction and other techniques (H03M13/31 and H03M13/33 take precedence) · CPC title

• H04L1/0045 Primary

  Arrangements at the receiver end · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H04L1/0042

  Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence) · CPC title

• H03M13/3905

  Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding · CPC title