Data recovery system for memory devices

Patent metadata

Field	Value
Publication number	US-11403169-B2
Application number	US-202017116969-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Dec 9, 2020
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).

First claim

What is claimed is:

1. A system comprising:
at least one memory configured to store data in memory cells;
a buffer configured to store data read from the memory cells; and
at least one processing device configured to:
read first data from a location in the memory;
store the first data in the buffer;
detect one or more errors in the first data;
in response to detecting the errors in the first data, write a data pattern to the location in the memory;
read the data pattern from the location in the memory;
identify at least one failing bit in the read data pattern; and
in response to identifying the failing bit, correcting the identified failing bit in the stored first data to provide corrected data.

2. The system of claim 1 , wherein the first data is read in response to receiving a read command from a host device, and the processing device is further configured to send the corrected data to the host device in reply to the read command.

3. The system of claim 2 , wherein:
the errors detected in the first data include an error caused by the failing bit, and at least one other bit error; and
the processing device is further configured to correct the other bit error using an error correction code prior to sending the corrected data to the host device.

4. The system of claim 1 , wherein:
detecting the errors in the first data includes detecting the errors using an error correction code, and determining that the detected errors exceed a correction capability of the error correction code; and
the processing device is further configured to write the corrected data to the location in the memory.

5. The system of claim 1 , further comprising an error correction code (ECC) decoder, wherein the ECC decoder is configured to detect the errors in the first data.

6. The system of claim 1 , wherein the identified failing bit is a stuck bit, and the processing device is further configured to:
determine a bit location of the stuck bit in the read data pattern;
determine a state of the stuck bit in the read data pattern;
determine a state of a bit at the bit location in the first data; and
determine that the state of the stuck bit in the read data pattern matches the state of the bit in the first data.

7. The system of claim 1 , wherein the failing bit is a stuck bit due to a defective one of the memory cells from which the first data is read.

8. The system of claim 1 , further comprising at least one sensor, wherein the processing device is further configured to:
receive sensor data from the sensor; and
select, based on the sensor data, the data pattern for writing to the location in the memory.

9. The system of claim 1 , wherein the processing device is further configured to, in response to detecting the errors in the first data, change a timing for at least one of writing the data pattern, or reading the data pattern.

10. A method comprising:
reading data from a location in a memory;
detecting an error in the read data;
in response to detecting the error, writing at least one data pattern to the location in the memory;
reading the data pattern from the location in the memory;
identifying, based on reading the data pattern, at least one bit error; and
in response to identifying the bit error, correcting the bit error in the read data to provide corrected data.

11. The method of claim 10 , further comprising writing the corrected data to the location in the memory.

12. The method of claim 11 , wherein the corrected data includes one or more other bit errors, the method further comprising correcting the other bit errors prior to writing the corrected data.

13. The method of claim 12 , wherein the identified bit error in the read data pattern is a stuck bit, and the other bit errors are corrected using an error correction code (ECC).

14. The method of claim 10 , wherein the read data is included in a page of data read from the memory, the method further comprising:
in response to identifying the bit error, changing a mapping of the page, or retiring the page.

15. The method of claim 10 , wherein:
the memory is included in a memory device; and
writing the data pattern is further in response to determining that a number of failed bits in the read data exceeds an error correction capability of the memory device.

16. The method of claim 10 , wherein the data is read from the location in the memory in response to receiving a read command from a host device, the method further comprising sending the corrected data to the host device in reply to the read command.

17. The method of claim 10 , wherein:
writing the data pattern includes writing a first pattern, and writing a second pattern;
reading the data pattern includes reading the first pattern, and reading the second pattern;
writing the second pattern is performed in response to determining that the read first pattern does not include bit errors; and
identifying the bit error is based on reading the second pattern.

18. The method of claim 17 , wherein the second pattern is an inverse of the first pattern.

19. A non-transitory computer-readable medium storing instructions which, when executed on at least one processing device, cause the at least one processing device to, in response to receiving a read command from a host device:
read data from memory;
detect an error in the read data;
in response to detecting the error, write at least one data pattern to the memory;
read the data pattern from the memory;
identify, based on reading the data pattern, at least one stuck bit;
in response to identifying the stuck bit, correct the read data to provide corrected data; and
send the corrected data to the host device.

20. The non-transitory computer-readable medium of claim 19 , wherein the instructions further cause the at least one processing device to:
determine an age or extent of use of the memory based on at least one of a counter, or an output from an artificial neural network; and
select, based on the determined age or extent of use, the data pattern for writing to the memory.

Assignees

• Micron Technology Inc

Inventors

• Fackenthal Richard Edward
• Eilert Sean S

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G11C2029/0411

  Online error correction · CPC title