Electromagnetic interference suppression circuit, method for driving same, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11398174-B2
Application number	US-202016999119-A
Country	US
Kind code	B2
Filing date	Aug 21, 2020
Priority date	Nov 25, 2019
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

An electromagnetic interference suppression circuit, a driving method thereof, and an electronic apparatus are provided. In the electromagnetic interference suppression circuit, a signal generating sub-circuit may generate a plurality of parallel target sequence signals, each with a period greater than a period threshold and a quantity of target sequence signals greater than a quantity threshold; and a frequency generating sub-circuit may output a frequency-jittered drive signal, for driving a switch mode power supply to operate, to the switch mode power supply under the control of the plurality of parallel target sequence signals.

First claim

What is claimed is:

1. An electromagnetic interference suppression circuit, comprising: a signal generating sub-circuit and a frequency generating sub-circuit; wherein
the signal generating sub-circuit is connected to a signal source, a clock signal terminal, and the frequency generating sub-circuit respectively, and is configured to output a plurality of parallel target sequence signals to the frequency sub-circuit in response to an initial signal provided by the signal source and a clock signal provided by the clock signal terminal, each of the target sequence signals having a period greater than a period threshold, and a quantity of target sequence signals being greater than a quantity threshold; and
the frequency generating sub-circuit is connected to a first power supply terminal and further connected to a switch mode power supply, and is configured to output a frequency-jittered drive signal to the switch mode power supply in response to the plurality of parallel target sequence signals and a first power supply signal provided by the first power supply terminal, the drive signal being intended to drive the switch mode power supply to operate.

2. The electromagnetic interference suppression circuit according to claim 1 , wherein the signal generating sub-circuit comprises: a first sequence generator and a decoder; wherein
the decoder comprises a plurality of input terminals and a plurality of output terminals, a quantity of input terminals of the decoder being less than the quantity threshold, and a quantity of output terminals of the decoder being greater than the quantity threshold;
the first sequence generator is connected to the signal source, the dock signal terminal, and the plurality of input terminals of the decoder respectively, and is configured to output a plurality of parallel initial sequence signals to the decoder by the plurality of input terminals of the decoder in response to the initial signal and the dock signal, each of the initial sequence signals has a period greater than the period threshold; and
the plurality of output terminals of the decoder are connected to the frequency generating sub-circuit, and the decoder is configured to output the plurality of parallel target sequence signals to the frequency generating sub-circuit in response to the plurality of parallel initial sequence signals.

3. The electromagnetic interference suppression circuit according to claim 2 , wherein the first sequence generator comprises: a plurality of D flip-flops and a logic gate unit; wherein
clock signals interfaces of the plurality of D flip-flops are all connected to the clock signal terminal, and an input terminal of a first D flip-flop of the D flip-flops is connected to the signal source and an output terminal of the logic gate unit, an output terminal of each of the D flip-flops except the first D flip-flop is connected to an output terminal of a previous D flip-flop thereof, and the output terminal of each of the D flip-flops is connected to an input terminal of the logic gate unit; and
the output terminal of the logic gate unit is further connected to the plurality of input terminals of the decoder, and is configured to generate the plurality of parallel initial sequence signals based on signals output by the output terminals of the plurality of D flip-flops.

4. The electromagnetic interference suppression circuit according to claim 3 , wherein the first sequence generator comprises ten D flip-flops; and the logic gate unit comprises; seven NOR gates, four NOT gates, one AND gate, one XOR gate, and one OR gate; wherein
the output terminal of the first D flip-flop and the output terminal of a second D flip-flop of the D flip-flops are connected to an input terminal of a first NOR gate, and the output terminals of a third D flip-flop to a sixth D flip-flop of the flip-flops are connected to an input terminal of a second NOR gate, output terminals of a seventh D flip-flop to a tenth D flip-flop of the D flip-flops are connected to an input terminal of a third NOR gate, and the output terminal of a seventh D flip-flop and the output terminal of a tenth D flip-flop are connected to an input terminal of the XOR gate;
an output terminal of the first NOR gate, an output terminal of the second NOR gate, and an output terminal of the third NOR gate are all connected to an input terminal of the AND gate, an output terminal of the AND gate or an output terminal of the XOR gate is connected to an input terminal of the OR gate, and an output terminal of the OR gate is connected to the input terminal of the first D flip-flop;
the output terminal of the first D flip-flop is further connected to an input terminal of a fourth NOR gate, the output terminal of the second D flip-flop is further connected to an input terminal of a fifth NOR gate, the output terminal of the third D flip-flop is further connected to an input terminal of a sixth NOR gate, the output terminal of the fourth D flip-flop is further connected to an input terminal of a seventh NOR gate, and the input terminals of the fourth NOR gate to the seventh NOR gate are further connected to the initial signal terminal; and
an input terminal of a first NOT gate is connected to the output terminal of the fourth NOR gate and the input terminal of the decoder, an input terminal of a second NOT gate is connected to the output terminal of the fifth NOR gate and the input terminal of the decoder, an input terminal of a third NOT gate is connected to the output terminal of the sixth NOR gate and the input terminal of the decoder, and an input terminal of a fourth NOT gate is connected to the output terminal of the seventh NOR gate and the input terminal of the decoder.

5. The electromagnetic interference suppression circuit according to claim 1 , wherein the signal generating sub-circuit comprises: a second sequence generator; wherein
the second sequence generator comprises an input terminal and a plurality of output terminals, a quantity of output terminals of the second sequence generator being greater than the quantity threshold; and
the input terminal of the second sequence generator is connected to the signal source and the clock signal terminal respectively, the plurality of output terminals of the second sequence generator are connected to the frequency generating sub-circuit, and the second sequence generator is configured to generate the plurality of parallel target sequence signals in response to the initial signal and the clock signal, and to output the plurality of parallel target sequence signals to the frequency generating sub-circuit by the plurality of output terminals of the second sequence generator.

6. The electromagnetic interference suppression circuit according to claim 1 , wherein the frequency generating sub-circuit comprises: a current providing unit and a frequency generating unit; wherein
the current providing unit is connected to the first power supply terminal, the signal generating sub-circuit, and the frequency generating unit respectively, and is configured to output a drive current to the frequency generating unit in response to the plurality of parallel target sequence signals and the first power supply signal; and
the frequency generating unit is further connected to the switch mode power supply, and is configured to generate the frequency-jittered drive signal under the driving of the drive current and output the frequency-jittered drive signal to the switch mode power supply.

7. The electromagnetic interference suppression circuit according to claim 6 , wherein the current providing unit is further connected to a reference power supply terminal, and is configured to output the drive current to the frequency generating unit based on the reference power supply signal provided by the refer

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Xiaoshi
• Wang Jianjun
• Chen Zejun
• Wang Rui

Classifications

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G09G2330/025

  Reduction of instantaneous peaks of current · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title