Storing memory array operational information in non-volatile subarrays

Patent metadata

Field	Value
Publication number	US-11392468-B2
Application number	US-201916444533-A
Country	US
Kind code	B2
Filing date	Jun 18, 2019
Priority date	Sep 16, 2016
Publication date	Jul 19, 2022
Grant date	Jul 19, 2022

Abstract

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

First claim

What is claimed is:

1. A method, comprising:
accessing a first portion of a memory array according to a set of access instructions for the memory array received from a host device, wherein the set of access instructions comprises commands and addresses of one or more non-volatile memory cells of the first portion of the memory array, and wherein the first portion of the memory array is configured to store data associated with the set of access instructions received from the host device;
storing, in a set of non-volatile memory cells of a second portion of the memory array, a representation of a pattern of the set of access instructions received from the host device, the second portion of the memory array comprising a subarray of the memory array; and
determining that a first failure associated with the memory array has occurred based at least in part on accessing the first portion of the memory array.

2. The method of claim 1 , further comprising:
storing, at the second portion of the memory array, information associated with the first failure based at least in part on determining that the first failure has occurred.

3. The method of claim 2 , further comprising:
determining that a second failure has occurred based at least in part on accessing the first portion of the memory array; and
accessing the stored information associated with the first failure based at least in part on determining that the second failure has occurred.

4. The method of claim 1 , further comprising:
receiving a trigger to enter a test mode, wherein the trigger comprises an indication to store the set of access instructions in the second portion of the memory array.

5. The method of claim 4 , further comprising:
refraining from storing the representation of the pattern of the set of access instructions in the second portion of the memory array until the trigger to enter the test mode is received.

6. The method of claim 1 , further comprising:
receiving a first flag from an application that has experienced an operating failure, wherein the first flag comprises an indication to store the set of access instructions in the second portion of the memory array.

7. The method of claim 1 , further comprising:
receiving a second flag from an error correction code component that has determined that a predetermined number of error correcting code (ECC) errors has occurred, wherein the second flag comprises an indication to store the set of access instructions in the second portion of the memory array.

8. The method of claim 1 , further comprising:
accessing the second portion based at least in part on storing the representation of the pattern of the set of access instructions.

9. The method of claim 1 , wherein accessing the first portion and storing the representation of the pattern of the set of access instructions in the second portion occur at a same time.

10. An apparatus, comprising:
a first plurality of non-volatile memory cells in a first portion of a memory array, the first portion of the memory array configured to store data associated with a set of access instructions received from a host device;
a second plurality of non-volatile memory cells in a second portion of the memory array different than the first portion, the second portion of the memory array comprising a subarray of the memory array, the second portion of the memory array configured to store a representation of a pattern of the set of access instructions received from the host device, wherein a respective access instruction comprises a command and an address of one or more of the first plurality of non-volatile memory cells of the first portion of the memory array;
an array driver in electronic communication with the memory array and operable to store access instructions for the memory array; and
a sense component in electronic communication with the memory array and the array driver.

11. The apparatus of claim 10 , wherein the array driver comprises:
a counter to track which of the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells were last written.

12. An apparatus, comprising:
a first plurality of non-volatile memory cells in a first portion of a memory array;
a second plurality of non-volatile memory cells in a second portion of the memory array different than the first portion;
an array driver in electronic communication with the memory array and operable to store access instructions for the memory array; and
a sense component in electronic communication with the memory array and the array driver, wherein the array driver comprises:
a command predecoder to map a plurality of signals associated with the access instructions and received at the array driver to a binary representation of the access instructions.

13. The apparatus of claim 10 , wherein the array driver comprises:
a set of amplifiers in electronic communication with the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells, wherein the set of amplifiers are operable to amplify received signals to store the access instructions at the second plurality of non-volatile memory cells.

14. The apparatus of claim 10 , further comprising:
an error correction code component to determine that a predetermined number of error correcting code (ECC) errors has occurred.

15. An apparatus, comprising:
a memory array comprising a plurality of memory cells;
an array driver; and
a controller in electronic communication with the memory array and the array driver, wherein the controller is operable to cause the apparatus to:
access a first portion of a memory array according to a set of access instructions for the memory array received from a host device, wherein the set of access instructions comprises commands and addresses of one or more non-volatile memory cells of the first portion of the memory array, and wherein the first portion of the memory array is configured to store data associated with the set of access instructions received from the host device;
store, in a set of non-volatile memory cells of a second portion of the memory array, a representation of a pattern of the set of access instructions received from the host device, the second portion of the memory array comprising a subarray of the memory array; and
determine that a first failure associated with the memory array has occurred based at least in part on accessing the first portion of the memory array.

16. The apparatus of claim 15 , wherein the controller is further operable to:
store an indication of the first failure in the second portion of the memory array based at least in part on determining that the first failure has occurred.

17. The apparatus of claim 16 , wherein the indication of the first failure comprises a temperature of the memory array at a time of the first failure, a value indicating a number of access operations performed on the memory array at the time of the first failure, the set of access instructions for the memory array at the time of the first failure, a value indicating a duration between access operations at the time of the first failure, or a combination thereof.

18. The apparatus of claim 16 , wherein the controller is further operable to:
determine that a second failure has occurred based at least in part on accessing the first portion of the memory array; and
retrieve the stored indication of the first failure based at least in part on determining that the second failure has occurred.

19. The apparatus of claim 16 ,

Assignees

• Micron Technology Inc

Inventors

• Kawamura Christopher John
• Derner Scott James
• Ingalls Charles L

Classifications

• G11C29/4401 Primary

  for self repair · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title