Display device and method for manufacturing the display device

Patent metadata

Field	Value
Publication number	US-11392004-B2
Application number	US-201917291663-A
Country	US
Kind code	B2
Filing date	Nov 25, 2019
Priority date	Dec 6, 2018
Publication date	Jul 19, 2022
Grant date	Jul 19, 2022

Abstract

The manufacturing yield of a display device is improved. The resistance of a display device to ESD is increased. The display device includes a substrate, a display portion, a connection terminal, a first wiring, and a second wiring. The first wiring is electrically connected to the connection terminal and includes a portion positioned between the connection terminal and the display portion. The second wiring is electrically connected to the connection terminal, is positioned between the connection terminal and an end portion of the substrate, and includes a portion in which a side surface is exposed at an end portion of the substrate. The display portion includes a transistor. The transistor includes a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer and the second wiring include a metal oxide.

First claim

The invention claimed is:

1. A display device comprising a substrate, a display portion, a connection terminal, a first wiring, and a second wiring,
wherein the first wiring is electrically connected to the connection terminal and comprises a portion positioned between the connection terminal and the display portion,
wherein the second wiring is electrically connected to the connection terminal, is positioned between the connection terminal and an end portion of the substrate, and comprises a portion in which an end surface is exposed at the end portion of the substrate,
wherein the display portion comprises a transistor,
wherein the transistor comprises a semiconductor layer, a gate insulating layer, and a gate electrode,
wherein the semiconductor layer and the second wiring comprise a metal oxide,
wherein the semiconductor layer comprises a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode, and
wherein the second region and the second wiring have lower resistances than the first region.

2. The display device according to claim 1 ,
wherein the semiconductor layer and the second wiring are provided on the same plane and comprise the same metal element.

3. The display device according to claim 1 ,
wherein the second wiring has a higher resistance than the first wiring.

4. The display device according to claim 1 , further comprising:
a third wiring electrically connected to the transistor,
wherein the third wiring and the first wiring are provided on the same plane and comprise the same metal element.

5. The display device according to claim 1 ,
wherein the connection terminal comprises part of the first wiring.

6. The display device according to claim 1 , further comprising:
an FPC electrically connected to the connection terminal,
wherein the FPC comprises a portion covering the exposed end surface of the second wiring.

7. The display device according to claim 1 ,
wherein the substrate comprises a first portion overlapping with the first wiring and a second portion overlapping with the connection terminal and the second wiring,
wherein the first portion is bent so that the first wiring is on an outer side, and
wherein the second portion comprises a region overlapping with the first wiring or the display portion.

8. A display device comprising a substrate, a display portion, a connection terminal, a first wiring, and a second wiring,
wherein the first wiring is electrically connected to the connection terminal and comprises a portion positioned between the connection terminal and the display portion,
wherein the second wiring is electrically connected to the connection terminal, is positioned between the connection terminal and an end portion of the substrate, and comprises a portion in which an end a cidc surface is exposed at the end portion of the substrate,
wherein the display portion comprises a transistor,
wherein the transistor comprises a semiconductor layer, a gate insulating layer, and a gate electrode, and
wherein the semiconductor layer and the second wiring are formed by processing the same oxide semiconductor film,
wherein the semiconductor layer comprises a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode, and
wherein the second region and the second wiring have lower resistances than the first region.

9. The display device according to claim 8 ,
wherein the semiconductor layer and the second wiring are provided on the same plane.

10. The display device according to claim 8 ,
wherein the second wiring has a higher resistance than the first wiring.

11. The display device according to claim 8 , further comprising:
a third wiring electrically connected to the transistor,
wherein the third wiring and the first wiring are provided on the same plane and comprise the same metal element.

12. The display device according to claim 8 ,
wherein the connection terminal comprises part of the first wiring.

13. The display device according to claim 8 , further comprising:
an FPC electrically connected to the connection terminal,
wherein the FPC comprises a portion covering the exposed end surface of the second wiring.

14. The display device according to claim 8 ,
wherein the substrate comprises a first portion overlapping with the first wiring and a second portion overlapping with the connection terminal and the second wiring,
wherein the first portion is bent so that the first wiring is on an outer side, and
wherein the second portion comprises a region overlapping with the first wiring or the display portion.

15. A method for manufacturing a display device comprising:
forming a transistor comprising a semiconductor layer, a plurality of connection terminals, and a wiring electrically connecting the plurality of connection terminals over a substrate;
cutting part of the substrate and part of the wiring to isolate the plurality of connection terminals electrically; and
connecting an FPC to the plurality of connection terminals,
wherein the semiconductor layer and the wiring are formed by processing the same metal oxide film,
wherein the semiconductor layer comprises a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode, and
wherein the second region and the second wiring have lower resistances than the first region.

Assignees

• Semiconductor Energy Lab

Inventors

• Okazaki Kenichi
• Shima Yukinori
• Kurosaki Daisuke
• Nakada Masataka

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/01

  Manufacture or treatment · CPC title

• G09F9/30

  in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) · CPC title