Modular I/O configurations for edge computing using disaggregated chiplets

Patent metadata

Field	Value
Publication number	US-11388054-B2
Application number	US-201916723118-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Apr 30, 2019
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

Various approaches for deployment and use of configurable edge computing platforms are described. In an edge computing system, an edge computing device includes hardware resources that can be composed from a configuration of chiplets, as the chiplets are disaggregated for selective use and deployment (for compute, acceleration, memory, storage, or other resources). In an example, configuration operations are performed to: identify a condition for use of the hardware resource, based on an edge computing workload received at the edge computing device; obtain, determine, or identify properties of a configuration for the hardware resource that are available to be implemented with the chiplets, with the configuration enabling the hardware resource to satisfy the condition for use of the hardware resource; and compose the chiplets into the configuration, according to the properties of the configuration, to enable the use of the hardware resource for the edge computing workload.

First claim

What is claimed is:

1. An edge computing device in an edge computing system, comprising:
at least one hardware resource, the hardware resource composed from a configuration of a plurality of chiplets, wherein the chiplets provide disaggregated portions of the hardware resource, including a plurality of disaggregated input/output (I/O) modules, and the chiplets comprise a dedicated chiplet that includes I/O controller logic; and
circuitry configured to perform operations to:
identify a condition for use of the hardware resource, based on an edge computing workload received at the edge computing device;
identify the hardware resource as available in the edge computing device to be used for the edge computing workload according to the configuration;
obtain properties of a configuration for the hardware resource that are available to be implemented with the chiplets, the configuration enabling the hardware resource to satisfy the condition for use of the hardware resource;
compose the chiplets into the configuration, according to the properties of the configuration, to enable the use of the hardware resource for the edge computing workload,
wherein deployment of the chiplets implement a topology to the disaggregated I/O modules according to the properties of the configuration, wherein the I/O controller logic controls I/O connections of the disaggregated I/O modules to provide communications between the disaggregated portions of the hardware resource and achieve hardware modularity for the hardware resource;
verify the configuration of the chiplets in the hardware resource, wherein the chiplets provide attestation for the use of the hardware resource with the edge computing workload according to the configuration, wherein each chiplet contains logic to provide cryptographic device identity, attestation, and data encryption, the logic producing an attestation key;
use the attestation key to identify a plurality of chiplet configurations and provide the attestation to a verifier that contains a policy describing at least one of acceptable or unacceptable configurations; and
determine and save the properties of the configuration for the hardware resource that are available to be implemented with the chiplets in order to reuse the configuration with a subsequent edge computing workload.

2. The edge computing device of claim 1 , wherein the hardware resource comprises at least one of:
compute resources;
pooled acceleration resources;
pooled memory resources; or
pooled storage resources.

3. The edge computing device of claim 2 ,
wherein composition of the chiplets into the configuration produces a virtual edge appliance for handling the edge computing workload on behalf of a tenant, and
wherein the virtual edge appliance provides use of:
a portion of accelerator components from the pooled acceleration resources,
a portion of compute components from the compute resources,
a portion of the memory from the pooled memory resources, and
a portion of the storage from the pooled storage resources.

4. The edge computing device of claim 1 ,
wherein the hardware resource comprises a configurable resource, and
wherein the circuitry is further configured to identify a configuration for the configurable resource and load the configuration onto the configurable resource.

5. The edge computing device of claim 4 , wherein the configurable resource comprises field-programmable gate array (FPGA) circuitry.

6. The edge computing device of claim 1 , wherein the circuitry is provided from a modular fabric, wherein the modular fabric is configured to coordinate the chiplets for use as a virtual computing platform.

7. The edge computing device of claim 6 , wherein the hardware resource includes a chiplet I/O interface to the modular fabric, the chiplet I/O interface configured to enable registration of the properties of the chiplets, manage hardware partitions of the chiplets, and connect the chiplets to the modular fabric.

8. The edge computing device of claim 6 , wherein the modular fabric is further configured to implement logic to:
perform discovery and registration of the chiplets;
identify available compositions of the chiplets; and
enable a user software stack to discover functionality provided for the chiplets.

9. The edge computing device of claim 6 , wherein the modular fabric is further configured to implement logic to:
create a virtual partition of at least a portion of the chiplets based on association with a particular tenant, and a service level agreement associated with the particular tenant;
wherein the circuitry is further configured to map a portion of the chiplets of the hardware resource to the virtual partition.

10. The edge computing device of claim 6 , wherein the modular fabric is further configured to implement logic to:
verify an identity and configuration of the respective chiplets.

11. The edge computing device of claim 6 , wherein the modular fabric is further configured to implement logic to:
monitor and enforce the configuration of the chiplets in the hardware resource, based on a composed node flavor of the virtual computing platform for a particular workload to be processed by the edge computing device.

12. The edge computing device of claim 11 ,
wherein the composed node flavor is one of a plurality of composed node flavors,
wherein respective node flavors of the plurality of composed node flavors correspond to respective types of workloads to be processed by the edge computing device, and
wherein the respective node flavors provide variations in type and amount of resources used for processing the respective types of workloads.

13. The edge computing device of claim 1 , wherein:
the logic comprises Device Identity Composition Engine (DICE) Root-of-trust logic (ROT), and
to verify the configuration of the chiplets in the hardware resource and provide attestation for the use of the hardware resource with the edge computing workload according to the configuration, the circuitry is further configured to:
check that each chiplet has reported its identity and has attested to a particular configuration of the chiplet as a condition of startup and arrangement in the configuration.

14. The edge computing device of claim 1 , the circuitry further configured to perform operations to:
verify security of the chiplets in the hardware resource, wherein security verifications include polling an internal bus to determine if an expected number, type and configuration of chiplets exists.

15. A method performed by an edge computing device, the edge computing device comprising at least one hardware resource composed from a configuration of a plurality of chiplets, wherein the chiplets provide disaggregated portions of the hardware resource, including a plurality of disaggregated input/output (I/O) modules, and the chiplets comprise a dedicated chiplet that includes I/O controller logic, and the method comprising:
identifying a condition for use of the hardware resource, based on an edge computing workload received at the edge computing device;
identifying the hardware resource as available in the edge computing device to be used for the edge computing workload according to the configuration;
obtain properties of a configuration for the hardware resource that is available to be implemented with the chiplets, the configuration enabling the hardware resource to satisfy the condition for use of the hardware resource;
composing the chiplets into the configuration, according to the properties of the configuration, to enable the use of the hardware resource for the edge computing wo

Assignees

• Intel Corp

Inventors

• Guim Bernat Francesc
• Doshi Kshitij Arun
• Smith Ned M
• Verrall Timothy
• Qureshi Uzair

Classifications

• H04L67/51 Primary

  Discovery or management thereof, e.g. service location protocol [SLP] or web services · CPC title

• H04L47/781

  Centralised allocation of resources · CPC title

• H04L67/289

  Intermediate processing functionally located close to the data consumer application, e.g. in same machine, in same home or in same sub-network · CPC title

• G06F9/5061

  Partitioning or combining of resources · CPC title

• H04L63/0435

  wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption (cryptographic mechanisms or cryptographic arrangements for symmetric key encryption H04L9/06) · CPC title