Semiconductor device including data storage material pattern

Patent metadata

Field	Value
Publication number	US-11387410-B2
Application number	US-202016800123-A
Country	US
Kind code	B2
Filing date	Feb 25, 2020
Priority date	Jun 7, 2019
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a base structure comprising a semiconductor substrate;
a first conductive structure on the base structure, and extending in a first direction, the first conductive structure comprising lower layers, and at least one among the lower layers comprising carbon;
a buffer layer on a first portion of a top surface of the first conductive structure;
an interlayer insulating layer on a top surface of the buffer layer;
a data storage pattern on a second portion of the top surface of the first conductive structure, and penetrating through the interlayer insulating layer and the buffer layer;
an intermediate conductive pattern on the data storage pattern, and comprising intermediate layers, at least one among the intermediate layers comprising carbon;
a switching pattern on the intermediate conductive pattern;
a switching upper electrode pattern on the switching pattern, and comprising carbon;
a second conductive structure on the switching upper electrode pattern, and extending in a second direction intersecting the first direction; and
a hole spacer between the interlayer insulating layer and at least a portion of a side surface of the data storage pattern,
wherein the buffer layer includes a material different from a material of the interlayer insulating layer,
wherein the buffer layer is between a bottom surface of the interlayer insulating layer and the first portion of the top surface of the first conductive structure, and
wherein the buffer layer extending in the first direction parallel to the top surface of the first conductive structure between the first conductive structure and the data storage pattern.

2. The semiconductor device of claim 1 , wherein a bottom surface of the hole spacer is higher than a bottom surface of the data storage pattern in which a phase change memory material is included, and
wherein the top surface of the buffer layer is at a lower level than a center between the top surface of the first conductive structure and a top surface of the data storage pattern.

3. The semiconductor device of claim 1 , wherein the hole spacer penetrates into the top surface of the buffer layer, and
wherein a bottom surface of the hole spacer is lower than the top surface of the buffer layer.

4. The semiconductor device of claim 1 , further comprising a planarization-stop layer interposed between the buffer layer and the interlayer insulating layer,
wherein the hole spacer is interposed between a side surface of the planarization-stop layer and the side surface of the data storage pattern.

5. The semiconductor device of claim 1 , further comprising an etch-stop layer on the interlayer insulating layer,
wherein the hole spacer is interposed between a side surface of the etch-stop layer and the side surface of the data storage pattern.

6. The semiconductor device of claim 5 , further comprising a planarization-stop layer interposed between the etch-stop layer and the intermediate conductive pattern,
wherein the hole spacer is interposed between a side surface of the planarization-stop layer and the side surface of the data storage pattern.

7. The semiconductor device of claim 6 , wherein the data storage pattern extends upwardly, penetrates through the etch-stop layer and the planarization-stop layer, and physically contacts the intermediate conductive pattern.

8. The semiconductor device of claim 1 , wherein the data storage pattern, in which a phase change memory material is included, further comprises a portion extending between a bottom surface of the hole spacer and a top surface of the first conductive structure.

9. The semiconductor device of claim 1 , wherein the switching upper electrode pattern comprises:
a first upper electrode layer comprising carbon; and
a second upper electrode layer on the first upper electrode layer.

10. The semiconductor device of claim 1 , wherein the hole spacer is spaced apart from the first conductive structure.

11. The semiconductor device of claim 1 , further comprising gap-fill insulating patterns on the base structure,
wherein the first conductive structure is between the gap-fill insulating patterns, and
wherein the interlayer insulating layer is on the buffer layer and the gap-fill insulating patterns.

12. A semiconductor device comprising:
a base structure comprising a semiconductor substrate;
a first conductive structure on the base structure, and extending in a first direction, the first conductive structure comprising lower layers, and at least one among the lower layers comprising carbon;
a buffer layer contacting a first portion of a top surface of the first conductive structure;
an interlayer insulating layer on a top surface of the buffer layer;
a data storage pattern on a second portion of the top surface of the first conductive structure, and penetrating through the interlayer insulating layer and the buffer layer;
an intermediate conductive pattern on the data storage pattern, and comprising intermediate layers, at least one among the intermediate layers comprising carbon;
a switching pattern on the intermediate conductive pattern;
a switching upper electrode pattern on the switching pattern, and comprising carbon; and
a second conductive structure on the switching upper electrode pattern, and extending in a second direction intersecting the first direction,
wherein a width of the at least one among the intermediate layers comprising carbon is greater than a width of the switching upper electrode pattern
wherein the buffer layer includes a material different from a material of the interlayer insulating layer,
wherein the buffer layer is between a bottom surface of the interlayer insulating layer and the first portion of the top surface of the first conductive structure, and
wherein the buffer layer extending in the first direction parallel to the top surface of the first conductive structure between the first conductive structure and the data storage pattern.

13. The semiconductor device of claim 12 , wherein, in the second direction, a width of the at least one among the lower layers comprising carbon is less than the width of the at least one among the intermediate layers comprising carbon, and is less than the width of the switching upper electrode pattern.

14. The semiconductor device of claim 12 , further comprising a hole spacer between the interlayer insulating layer and at least a portion of a side surface of the data storage pattern,
wherein a bottom surface of the hole spacer is higher than a bottom surface of the data storage pattern in which a phase change memory material is included, and
wherein the top surface of the buffer layer is at a lower level than a center between the top surface of the first conductive structure and a top surface of the data storage pattern.

15. The semiconductor device of claim 14 , wherein the side surface of the data storage pattern is on an entirety of a side surface of the hole spacer.

16. The semiconductor device of claim 14 , wherein the data storage pattern, in which a phase change memory material is included, further comprises a portion extending between the bottom surface of the hole spacer and a top surface of the first conductive structure.

17. A semiconductor device comprising:
a base structure comprising a semiconductor substrate;
a first conductive structure on the base structure, and extending in a first direction, the first conductive structure comprising a first lower layer, a second lower layer on the second lower layer, and a third lower layer on the secon

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jeonghee
• Park Kwangmin
• Park Jiho
• Oh Gyuhwan
• Lee Jungmoo
• Horii Hideki

Classifications

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title

• H01L45/1691

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic

• H01L45/1683

  Electricity · mapped topic

• H01L27/24

  Electricity · mapped topic