Trench gate depletion mode VDMOS device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11387349-B2
Application number	US-201917265587-A
Country	US
Kind code	B2
Filing date	Oct 14, 2019
Priority date	Oct 15, 2018
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

First claim

What is claimed is:

1. A trench gate depletion mode VDMOS device comprising:
a drain region being of a first conductive type;
a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer;
a channel region located around the gate insulating layer and being of the first conductive type;
a well region located on both sides of the trench gate and being of a second conductive type, wherein the first conductive type is a conductive type opposite to the second conductive type;
a source region located within the well region and being of the first conductive type;
a drift region located between the well region and the drain region, the drift region being of the first conductive type;
a second conductive type doped region located between the channel region and the drain region;
a first conductive type doped region located on both sides of the second conductive type doped region and located between the drift region and the drain region.

2. The trench gate depletion mode VDMOS device according to claim 1 , wherein first conductive type doped region has a higher doping concentration than the drift region.

3. The trench gate depletion mode VDMOS device according to claim 2 , wherein the drain region has a higher doping concentration than the first conductive type doped region.

4. The trench gate depletion mode VDMOS device according to claim 1 , wherein a bottom of the channel region extends into the second conductive type doped region.

5. The trench gate depletion mode VDMOS device according to claim 1 , wherein the second conductive type doped region has a lower doping concentration than the well region.

6. The trench gate depletion mode VDMOS device according to claim 1 , wherein the device further includes a body lead-out region of the second conductive type which is located in the well region.

7. The trench gate depletion mode VDMOS device according to claim 1 , wherein the material of the gate insulating layer is silicon oxide, and the material of the gate electrode is polysilicon.

8. The trench gate depletion mode VDMOS device according to claim 1 , wherein the first conductive type is N type and the second conductive type is P type.

9. The trench gate depletion mode VDMOS device according to claim 1 , wherein both the first conductive type doped region and the second conductive type doped region are super junction structures.

10. A method for manufacturing a trench gate depletion mode VDMOS device comprising:
providing a substrate which includes a first conductive type doped region and a drift region of a first conductive type on the first conductive type doped region;
etching the drift region to form a trench;
doping side walls of the trench to form a channel region in the trench;
doping impurities of a second conductive type into an area of the first conductive type doped region around a bottom of the trench, and thereby forming a second conductive type doped region within the first conductive type doped region; the first conductive type being a conductive type opposite to the second conductive type;
forming a gate insulating layer on an inner wall of the trench;
filling a remaining space of the trench to form a gate electrode;
doping impurities of the second conductive type on the surface of the drift region to form a well region at both sides of the trench;
doping impurities of the first conductive type into the well region, and thereby forming a source region.

11. The method according to claim 10 , wherein in providing the substrate, the first conductive type doped region is formed by an epitaxy process.

12. The method according to claim 10 , wherein providing the substrate includes epitaxilly forming the drift region on the first conductive type doped region.

13. The method according to claim 10 , wherein in etching the drift region to form the trench, the bottom of the trench reaches the first conductive type doped region.

14. The method according to claim 10 , wherein etching the drift region to form the trench is to etch after photoetching, and the remaining photoresist is used as a masking layer for doping the side walls of the trench and doping impurities of the second conductive type into the area of the first conductive type doped region around the bottom of the trench.

15. The method according to claim 10 , wherein in providing a substrate, the substrate is of the first conductive type and is used as a drain region, the drain region has a higher doping concentration than the first conductive type doped region, and the first conductive type doped region has a higher doping concentration than the drift region.

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Gu Yan
• Cheng Shikang
• Zhang Sen

Classifications

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/635

  having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/0297 Primary

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title