Circuit engine for managing memory meta-stability

Patent metadata

Field	Value
Publication number	US-11386010-B2
Application number	US-202017111207-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Sep 27, 2016
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

First claim

We claim:

1. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells;
a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank; and
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory bank, wherein the predetermined amount of time is related to a fill rate of the cache memory.

2. The memory device of claim 1 , wherein each of the first plurality of data words to be written into the memory bank is also written into the cache memory at substantially the same time.

3. The memory device of claim 2 , wherein the write verification operation associated with the data word comprises comparing the data word written into the memory bank with a corresponding copy of the data word written into the cache memory.

4. The method of claim 1 , wherein the predetermined amount of time is related to an amount of time required by stuck bits in intermediate states within the memory bank to relax into a final state.

5. The memory device of claim 1 , wherein the predetermined amount of time is programmable.

6. The memory device of claim 1 , wherein the predetermined amount of time is programmable and configured based on a programmable trim option.

7. The memory device of claim 1 , wherein the predetermined amount of time is a function of temperature.

8. A memory pipeline for performing a write operation in a memory device, the memory pipeline comprising:
an input register operable to receive a data word and an associated address to be written into a memory bank;
a write register of a first pipe-stage coupled to the input register and operable to receive the data word and the associated address from the input register in a first clock cycle, wherein the write register is further operable to perform a first attempt at writing said data word into the memory bank at a location corresponding to the associated address;
a delay register of a second pipe-stage coupled to the first write register and operable to receive the data word and the associated address from the write register in a second clock cycle, wherein the delay register is operable to write the data word and the associated address into an error buffer and is further operable to provide a delay cycle of a predetermined time period between the write register and a verify register; and
the verify register associated with a third pipe-stage, wherein the verify register is coupled to the delay register and is operable to receive the data word and the associated address from the delay register in a third clock cycle, and wherein the verify register is operable to perform a write verification operation associated with the data word after the data word is written into the memory bank.

9. The memory pipeline of claim 8 , wherein the write verification operation associated with the data word comprises comparing the data word written into the memory bank with a corresponding copy of the data word written into the error buffer.

10. The memory pipeline of claim 8 , wherein the predetermined time period is programmable.

11. The memory pipeline of claim 8 , wherein the predetermined time period is programmable and based on a timer delay.

12. The memory pipeline of claim 8 , wherein the predetermined amount of time is programmable and based on an “n” number of cycles.

13. The memory pipeline of claim 8 , wherein the predetermined amount of time is programmable and is based on a timer delay responsive to a determination that the memory pipeline is active or based on an “n” number of cycles responsive to a determination that the memory pipeline is inactive.

14. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells;
a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank; and
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a programmable period of time after the data word is written into the memory bank, wherein the programmable period of time is configurable based on a trim option.

15. The memory device of claim 14 , wherein each of the first plurality of data words to be written into the memory bank is also written into the cache memory at substantially the same time.

16. The memory device of claim 14 , wherein the cache memory comprises a first-in-first-out (FIFO) queue.

17. The memory device of claim 14 , wherein an elapsing of the programmable period of time is determined based on timestamps.

18. The memory device of claim 14 , wherein the programmable period of time is a function of temperature.

19. The memory device of claim 1 , wherein the cache memory comprises a first-in-first-out (FIFO) queue.

20. The memory device of claim 14 , wherein the predetermined amount of time is related to a fill rate of the cache memory.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Berger Neal
• Louie Benjamin
• Crudele Lester

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title