Device, method and system of error detection and correction in multiple devices

US11385288B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11385288-B2
Application numberUS-202017031716-A
CountryUS
Kind codeB2
Filing dateSep 24, 2020
Priority dateSep 27, 2019
Publication dateJul 12, 2022
Grant dateJul 12, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method, comprising: testing at least three devices, each device including a test chain having a plurality of positions storing test data, the testing including: detecting errors by: comparing test data in a last position of the test chain of each of the devices; and shifting test data in the test chains of each of the devices; and correcting errors by storing a result of the comparison in a first position of the test chains of each of the devices; and repeating the comparing and the shifting and storing until all the stored test data has been compared. 2. The method of claim 1 , comprising storing pieces of test data in test points. 3. The method of claim 2 , wherein the test points are registers or flip-flops. 4. The method of claim 2 , wherein the test data comprises binary words. 5. The method of claim 1 , wherein the test data comprises binary words, each binary word having a same size. 6. The method of claim 1 , wherein the test data comprises binary words of different sizes. 7. The method of claim 1 , wherein the devices each comprise a plurality of test chains. 8. The method of claim 1 , comprising testing more than three devices. 9. The method of claim 1 , wherein the at least three devices have a same structure and a same function. 10. The method of claim 1 , wherein the result of the comparison is a value stored in the last position of a test chain of two or more of the at least three devices prior to the shifting. 11. The method of claim 1 , comprising: responding to the result of the comparison indicating an error in one of the at least three devices by disregarding test results from the one of the at least three devices in subsequent comparisons. 12. The method of claim 11 , comprising: responding to a result of a subsequent comparison indicating the test data is different by generating an indication of a system failure. 13. A device, comprising: a comparator; and control circuitry coupled to the comparator, wherein the control circuitry, in operation, controls detecting and correcting of errors of at least three electronic circuits, each electronic circuit including a test chain having a plurality of positions storing test data, the detecting and correcting including: comparing test data in a last position of the test chain of each of the electronic circuits; and shifting test data in the test chains of each of the electronic circuits and storing a result of the comparison in a first position of the test chains of each of the electronic circuits, wherein the comparing and the shifting and storing are repeated until all the stored test data has been compared. 14. The device of claim 13 , wherein the control circuitry comprises at least three feedback loops, each coupling an output of the comparator and an input of the test chain of one of the three electronic circuits. 15. The device of claim 14 , wherein each feedback loop comprises a multiplexer. 16. The device of claim 13 , wherein the control circuitry, in operation: responds to the result of the comparison indicating an error in one of the at least three electronic circuits by disregarding test results from the one of the at least three electronic circuits in subsequent comparisons; and responds to a result of a subsequent comparison indicating the test data is different by generating an indication of a system failure. 17. A system, comprising: at least three electronic devices, each including a test chain having a plurality of positions storing test data; and testing circuitry coupled to the at least three electronic devices, wherein the testing circuitry, in operation, detects and corrects errors of the at least three electronic devices, the detecting and correcting including: comparing test data in a last position of the test chain of each of the at least three electronic devices; and shifting test data in the test chains of each of the at least three electronic devices and storing a result of the comparison in a first position of the test chains of each of the devices, wherein the comparing and the shifting and storing are repeated until all the stored test data has been compared. 18. The system of claim 17 , wherein the test chains comprise test points, which, in operation, store test data. 19. The system of claim 18 , wherein the test points are registers or flip-flops. 20. The system of claim 17 , wherein the test data comprises binary words. 21. The system of claim 17 , wherein the test data comprises binary words, each binary word having a same size. 22. The system of claim 17 , wherein the test data comprises binary words of different sizes. 23. The system of claim 17 , wherein the electronic devices each comprise a plurality of test chains. 24. The system of claim 17 , wherein the at least three electronic devices have a same structure and a same functionality. 25. The system of claim 17 , wherein the testing circuitry comprises a comparator and a plurality of feedback loops coupling one or more outputs of the comparator to inputs of the testing chains. 26. The system of claim 17 , wherein the result of the comparison is a value stored in the last position of a test chain of two or more of the at least three devices prior to the shifting. 27. The system of claim 17 , wherein the testing circuitry, in operation, responds to the result of the comparison indicating an error in one of the at least three electronic devices by disregarding test results from the one of the at least three electronic devices in subsequent comparisons. 28. The system of claim 27 , wherein the testing circuitry, in operation, responds to a result of a subsequent comparison indicating the test data is different by generating an indication of a system failure.

Assignees

Inventors

Classifications

  • Error detection by comparing the output of redundant processing systems · CPC title

  • Reconfiguring circuits for testing, e.g. LSSD, partitioning · CPC title

  • Soft error testing; Soft error rate evaluation; Single event testing · CPC title

  • Storing data, e.g. failure memory · CPC title

  • and the comparison itself uses redundant hardware · CPC title

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What does patent US11385288B2 cover?
A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The…
Who is the assignee on this patent?
St Microelectronics Sa
What technology area does this patent fall under?
Primary CPC classification G06F11/183. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 12 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).