Double-sided display panel and manufacturing method, driving circuit and driving method

US11380741B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11380741-B2
Application numberUS-201816343775-A
CountryUS
Kind codeB2
Filing dateOct 30, 2018
Priority dateApr 27, 2018
Publication dateJul 5, 2022
Grant dateJul 5, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel includes a plurality of display elements over a substrate, each including at least one first light-emitting element for emitting a first light out of a first light-emitting surface and at least one second light-emitting element for emitting a second light out of a second light-emitting surface opposing to the first light-emitting surface. Each first light-emitting element has a first light-emitting layer between two first electrodes, which are respectively transparent and reflective so that the first light can transmit out of the first light-emitting surface. Each second light-emitting element includes a second light-emitting layer between two second electrodes, which are respectively transparent and reflective so that the second light transmits out of the second light-emitting surface. The first and second light-emitting surface are below and over the substrate respectively. A driving circuit is configured to drive the display panel.

First claim

Opening claim text (preview).

The invention claimed is: 1. A driving circuit for driving a display panel, the display panel comprising: a substrate; and a plurality of display elements over the substrate, each comprising at least one first light-emitting element and at least one second light-emitting element, configured to respectively emit a first light out of a first light-emitting surface, and a second light out of a second light-emitting surface opposing to the first light-emitting surface, of the display panel, wherein: each of the at least one first light-emitting element comprises a first light-emitting layer sandwiched between two first electrodes, wherein the two first electrodes are configured to be respectively transparent and reflective so that the first light emitted by the first light-emitting layer transmits out of the first light-emitting surface of the display panel; each of the at least one second light-emitting element comprises a second light-emitting layer sandwiched between two second electrodes, wherein the two second electrodes are configured to be respectively transparent and reflective so that the second light emitted by the second light-emitting layer transmits out of the second light-emitting surface of the display panel; wherein: the first light-emitting surface is below the substrate; and the second light-emitting surface is over the substrate; the driving circuit comprising a pixel compensation circuit, wherein the pixel compensation circuit comprises a driving sub-circuit, a data writing sub-circuit, a power source control sub-circuit, a resetting sub-circuit, a capacitance element, and a compensation sub-circuit, wherein: the driving sub-circuit comprises a driving transistor, wherein a first electrode of the driving transistor is electrically coupled to a signal output terminal of the pixel compensation circuit; the data writing sub-circuit is electrically coupled to a gate line of a corresponding row, a data line of a corresponding column, and a second electrode of the driving transistor, respectively, and is configured to control whether or not to electrically connect the data line and the second electrode of the driving transistor under control of the gate line; the power source control sub-circuit is electrically coupled to a power source control terminal, a power source signal input terminal, and the second electrode of the driving transistor, respectively, and is configured to control whether or not to electrically connect the power source signal input terminal and the second electrode of the driving transistor under control of the power source control terminal; the resetting sub-circuit is electrically coupled to a resetting control terminal, a gate electrode of the driving transistor, and a first electric level input terminal, respectively, and is configured to control whether or not to electrically connect the gate electrode of the driving transistor and the first electric level input terminal under control of the resetting control terminal; the capacitance element comprises a first terminal and a second terminal, wherein the first terminal and the second terminal are electrically connected to the gate electrode of the driving transistor, and to the first electric level input terminal, respectively; the compensation sub-circuit is electrically coupled to the gate line, the gate electrode of the driving transistor, and the first electrode of the driving transistor, respectively, and is configured to control whether or not to electrically connect the gate electrode of the driving transistor and the first electrode of the driving transistor under control of the gate line. 2. The driving circuit of claim 1 , wherein: in each of the at least one first light-emitting element, the two first electrodes comprise a first anode and a first cathode, wherein: the first anode, the first light-emitting layer, and the first cathode are sequentially disposed over the substrate; the first anode comprises a first transparent conductive material; and the first cathode comprises a first reflecting conductive material; and in each of the at least one second light-emitting element, the two second electrodes comprise a second anode and a second cathode, wherein: the second anode, the second light-emitting layer, and the second cathode are sequentially disposed over the substrate; the second anode comprises a second reflecting conductive material; and the second cathode comprises a second transparent conductive material. 3. The driving circuit of claim 1 , wherein each of the plurality of display elements further comprises a driving circuit, configured to provide driving signals to each of the at least one first light-emitting element and each of the at least one second light-emitting element. 4. The driving circuit of claim 3 , wherein the driving circuit is arranged between a substrate and one of the two second electrodes that is reflective, configured such that an orthographic projection of the driving circuit on the substrate is at least partially overlapped with an orthographic projection of the one of the two second electrodes on the substrate. 5. The driving circuit of claim 3 , wherein the driving circuit comprises a pixel compensation circuit, having a signal output terminal thereof electrically coupled to each of the at least one first light-emitting element and each of the at least one second light-emitting element such that each of the at least one first light-emitting element and each of the at least one second light-emitting element receives substantially same driving signals from the pixel compensation circuit. 6. The driving circuit of claim 3 , wherein the driving circuit further comprises a first control circuit and a second control circuit, wherein: the first control circuit is electrically coupled to a signal output terminal of the pixel compensation circuit and the at least one first light-emitting element respectively, and is configured to control whether or not the signal output terminal of the pixel compensation circuit is electrically connected to the each of the at least one second light-emitting element; and the second control circuit is electrically coupled to the signal output terminal of the pixel compensation circuit and the at least one second light-emitting element respectively, and is configured to control whether or not the signal output terminal of the pixel compensation circuit is electrically connected to the each of the at least one second light-emitting element. 7. The driving circuit of claim 1 , wherein in each of the plurality of display elements, a number of the at least one first light-emitting element is different from a number of the at least one second light-emitting element. 8. The driving circuit of claim 1 , wherein in each of the plurality of display elements, a number of the at least one first light-emitting element is equal to a number of the at least one second light-emitting element, wherein: an area of a first light-emitting region formed by each of the at least one first light-emitting element is substantially equal to an area of a second light-emitting region formed by each of the at least one second light-emitting element. 9. The driving circuit of claim 8 , wherein each of the plurality of display elements consists of one first light-emitting element and one second light-emitting element. 10. The driving circuit of claim 1 , wherein the at least one first light-emitting element in each of the plurality of display elements together form a plurality of first light-emitting elements, and the at least one second light-emitting element in each of the plurality of display elements together form a plurality of second light-emitting elements, wherein:

Assignees

Inventors

Classifications

  • Active-matrix OLED [AMOLED] displays · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements · CPC title

  • Preventing or counteracting the effects of ageing · CPC title

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What does patent US11380741B2 cover?
A display panel includes a plurality of display elements over a substrate, each including at least one first light-emitting element for emitting a first light out of a first light-emitting surface and at least one second light-emitting element for emitting a second light out of a second light-emitting surface opposing to the first light-emitting surface. Each first light-emitting element has a …
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 05 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).