Memory arrays with vertical thin film transistors coupled between digit lines

Patent metadata

Field	Value
Publication number	US-11380388-B2
Application number	US-202117140540-A
Country	US
Kind code	B2
Filing date	Jan 4, 2021
Priority date	Aug 23, 2018
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

First claim

What is claimed is:

1. An apparatus comprising:
a hierarchical digit line structure comprising a first digit line at a first level, a second digit line at a second level that is different from the first level, and a third digit line at the first level;
a bus at the first level between the first digit line and the third digit line;
a memory cell comprising a planar transistor and a storage element, the planar transistor comprising a source and drain arranged horizontally and coupled between the first digit line and the storage element;
a vertical transistor comprising source and drain arranged vertically and coupled between the first and second digit lines; and
a local sense amplifier coupled to the first and third digit lines and the bus, wherein the local sense amplifier comprises a plurality of vertical thin film transistors at a third level between the first and second levels.

2. The apparatus of claim 1 , wherein the apparatus further comprises an additional memory cell comprising an additional planar transistor and an additional storage element.

3. The apparatus of claim 2 , wherein the additional planar transistor comprises a source and a drain arranged horizontally and coupled between the third digit line and the additional storage element.

4. The apparatus of claim 3 , wherein the additional planar transistor further comprises an additional vertical transistor comprising a source and drain arranged vertically and coupled between the second and third digit lines.

5. The apparatus of claim 1 , further comprising a main sense amplifier coupled to the second digit line.

6. The apparatus of claim 1 , wherein the storage element is between the first and second levels.

7. An apparatus comprising:
a hierarchical digit line structure comprising a first digit line at a first level and a second digit line at a second level that is different from the first level;
a memory array comprising a first group of memory cells coupled to the first digit line at the first level, wherein the first group of memory cells comprise planar transistors and storage elements, and a second group of memory cells coupled to the second digit line at the first level, wherein the second group of memory cells comprise planar transistors and storage elements; and
a local sense amplifier comprising:
a first vertical thin film transistor at a third level between the first and second levels, and
a second vertical thin film transistor at the third level.

8. The apparatus of claim 7 , further comprising a third digit line at the second level.

9. The apparatus of claim 8 , further comprising a bus at the second level.

10. The apparatus of claim 9 , wherein the bus is located between the second digit line and the third digit line at the second level.

11. The apparatus of claim 7 , wherein the first vertical thin film transistor is configured to selectively couple the bus to the first digit line.

12. The apparatus of claim 7 , wherein the second vertical thin film transistor configured to selectively couple the bus to the first digit line.

13. A method of forming an apparatus, the method of forming comprising:
forming a hierarchical digit line structure comprising a first digit line at a first level, a second digit line at a second level that is different from the first level, and a third digit line at the first level;
forming a bus at the first level between the first digit line and the third digit line;
forming a memory cell comprising a planar transistor and a storage element, the planar transistor comprising a source and drain arranged horizontally and coupled between the first digit line and the storage element;
forming a vertical transistor comprising source and drain arranged vertically and coupled between the first and second digit lines; and
forming a local sense amplifier coupled to the first and third digit lines and the bus, and wherein the local sense amplifier comprises a plurality of vertical thin film transistors at a third level between the first and second levels.

14. The method of forming of claim 13 , further comprising forming:
a main sense amplifier coupled to the second digit line.

15. The method of forming of claim 13 , further comprising forming an additional memory cell comprising an additional planar transistor and an additional storage element.

16. The method of forming of claim 15 , wherein forming the additional planar transistor comprises forming:
a source and a drain arranged horizontally and coupled between the third digit line and the additional storage element; and
an additional vertical transistor comprising a source and drain arranged vertically and coupled between the second and third digit lines.

Assignees

• Micron Technology Inc

Inventors

• Derner Scott J
• Ingalls Charles L

Classifications

• H10D30/6728

  Vertical TFTs · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• G11C11/4097 Primary

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title