Selective reading of memory with improved accuracy

Patent metadata

Field	Value
Publication number	US-11379286-B2
Application number	US-202016791674-A
Country	US
Kind code	B2
Filing date	Feb 14, 2020
Priority date	Mar 14, 2013
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.

First claim

The invention claimed is:

1. A memory device, comprising:
a memory array including a plurality of memory cells;
an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array; and
a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells;
a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on detecting the one or more error conditions associated with the reference value; and
a sense output circuit operable to:
compare the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal; and
output a data digit based at least in part on a comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.

2. The memory device of claim 1 , wherein:
the reference circuit is operable to generate the reference signal for the first mode; and
the self-reference circuit is operable to receive the self-reference value read from the at least one memory cell of the plurality of memory cells associated with a first read operation.

3. The memory device of claim 2 , wherein the self-reference circuit is operable to generate a self-reference signal based at least in part on the reference value.

4. The memory device of claim 3 , wherein the sense output circuit is operable to:
perform a first comparison of the reference value read from the at least one memory cell of the plurality of memory cells and the reference signal, and
perform a second comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.

5. The memory device of claim 4 , wherein the second comparison is performed after the first comparison.

6. The memory device of claim 4 , wherein the sense circuit is operable to output a data value based at least in part on the first comparison or the second comparison, and wherein the data value represents data stored in the at least one memory cell of the plurality of memory cells.

7. The memory device of claim 1 , wherein at least one of the plurality of memory cells comprises a spin-transfer torque (STT) magnetic tunnel junction (MTJ) memory cell.

8. The memory device of claim 7 , wherein the STT MJT memory cell is operable to store multi-level data digits that correspond to two or more different states of the STT MJT memory cell.

9. The memory device of claim 1 , wherein at least one of the plurality of memory cells comprises a magnetoresistive random access memory (MRAM) cell.

10. The memory device of claim 1 , wherein the sense circuit is operable to:
delay sending data associated with the first mode of the sense circuit to a memory controller.

11. A memory device, comprising:
a memory array including a plurality of memory cells;
an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array; and
a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells; and
a multiplexer operable to:
receive the reference signal and the reference value read from the at least one memory cell of the plurality of memory cells;
receive a signal indicating a detection of the one or more error conditions associated with the data read from at least one of the plurality of memory cells; and
output the reference signal, or the value read from the at least one memory cell, or both to the sense output circuit based at least in part on the received signal;
a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on detecting the one or more error conditions associated with the reference value; and
a sense output circuit operable to:
compare the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal; and
output a data digit based at least in part on a comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.

12. A memory device, comprising:
a memory array including a plurality of memory cells;
an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array; and
a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells;
a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on detecting the one or more error conditions associated with the reference value, wherein the self-reference circuit is operable to generate the self-reference value based at least in part on a second value read from a second memory cell of the plurality of memory cells during a reference read operation that occurs before the self-reference value is generated, wherein the second value read from the second memory cell includes the self-reference value and a third value read from the second memory cell during an additional reference read operation of the second memory cell; and

a sense output circuit operable to:
compare the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal; and
output a data digit based at least in part on a comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.

13. A memory device, comprising:
a memory array including a plurality of memory cells;
an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array; and
a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells;
a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on de

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Kinney Wayne
• Sandhu Gurtej S

Classifications

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G11C11/1677

  Verifying circuits or methods · CPC title