Voltage regulator circuit with current limiter stage

Patent metadata

Field	Value
Publication number	US-11378993-B2
Application number	US-202017030267-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Sep 23, 2020
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

Examples are disclosed herein that relate to automatically limiting an output current of a voltage regulator circuit responsive to detecting that the voltage regulator is in a current overload mode. In one example, a voltage regulator circuit includes an amplifier stage and a current limiter stage electrically connected to an output of the amplifier stage. The amplifier stage is configured to output a DC voltage based on a reference voltage and feedback from an output voltage. The current limiter stage is configured to operate in a quiescent mode and an overload mode. In the quiescent mode, the current limiter stage is configured to operate as a buffer stage that forms a closed feedback loop to an input of the amplifier stage. In the overload mode, the current limiter stage is configured to act as a current source that clamps an output current to a designated current.

First claim

The invention claimed is:

1. A voltage regulator circuit, comprising:
an amplifier stage configured to output a DC voltage based on a reference voltage and feedback from an output voltage of the voltage regulator circuit; and
a current limiter stage electrically connected to an output of the amplifier stage, the current limiter stage comprising a source follower transistor, wherein the current limiter stage is configured to operate in a quiescent operating mode and an overload operating mode, such that
in the quiescent operating mode, the source follower transistor is configured to operate as a buffer stage of the current limiter stage and forms a closed feedback loop that feeds back the output voltage of the voltage regulator circuit to an input of the amplifier stage, and
in the overload operating mode, the source follower transistor is configured to operate as a triode switch such that the current limiter stage acts as a current mirror that clamps an output current of the voltage regulator circuit to a designated current.

2. The voltage regulator circuit of claim 1 , wherein the source follower transistor comprises a source follower field effect transistor (FET) comprising a gate electrically connected to the output of the amplifier stage, and wherein the current limiter stage includes:
an output FET, wherein a gate of the output FET is electrically connected to a source of the source follower FET, wherein a source of the output FET is electrically connected to a power supply node, and wherein a drain of the output FET is electrically connected to an output node of the voltage regulator circuit, and
a current control stage electrically intermediate the power supply node and a drain of the source follower FET;
wherein the current limiter stage is configured to operate in the quiescent operating mode and the overload operating mode, such that
in the quiescent operating mode, the source follower FET and the output FET are configured to operate as the buffer stage that forms the closed feedback loop to feedback the output voltage of the voltage regulator circuit to the input of the amplifier stage, and
in the overload operating mode, the source follower FET is configured to act as the triode switch that electrically connects the current control stage to the gate of the output FET such that the output current of the voltage regulator circuit is clamped to the designated current that is controlled by the current control stage.

3. The voltage regulator circuit of claim 2 , wherein the current limiter stage further includes:
a source follower replica FET, wherein a source of the source follower replica FET is electrically connected to the current control stage, wherein a drain of the source follower replica FET is electrically connected to the drain of the source follower FET, and wherein the source follower replica FET is configured such that a drain-to-source voltage of the source follower replica FET is equal to a drain-to-source voltage of the source follower FET in the overload operating mode.

4. The voltage regulator circuit of claim 2 , wherein the current limiter stage further includes:
a first current source electrically connected to the power supply node and electrically intermediate the power supply node and the source of the source follower FET and the gate of the output FET.

5. The voltage regulator circuit of claim 2 , wherein the current limiter stage further includes:
a second current source electrically connected to the drain of the source follower FET.

6. The voltage regulator circuit of claim 2 , wherein the current control stage comprises one or more current control FETS.

7. The voltage regulator circuit of claim 6 , wherein the current control stage comprises a plurality of current control FETS in series.

8. The voltage regulator circuit of claim 6 , wherein the current control stage comprises a plurality of current control FETS connected via a plurality of switches operable to vary the designated current.

9. The voltage regulator circuit of claim 1 , wherein the buffer stage comprises a unity gain buffer stage.

10. The voltage regulator circuit of claim 1 , wherein the current limiter stage is configured to switch from operation in the quiescent operating mode to operation in the overload operating mode responsive to a short circuit at the output node.

11. The voltage regulator circuit of claim 1 , wherein the current limiter stage is configured to switch from operation in the quiescent operating mode to operation in the overload operating mode responsive to the amplifier stage outputting zero volts.

12. The voltage regulator circuit of claim 1 , wherein the current limiter stage is configured to switch from operation in the quiescent operating mode to operation in the overload operating mode responsive to the output current of the voltage regulator circuit being greater than a threshold current.

13. A voltage regulator circuit, comprising:
an amplifier stage configured to output a DC voltage based on a reference voltage and feedback of an output voltage of the voltage regulator circuit; and
a current limiter stage including:
a source follower field effect transistor (FET), wherein a gate of the source follower FET is electrically connected to an output of the amplifier stage,
an output FET, wherein a gate of the output FET is electrically connected to the source of the source follower FET, wherein the source of the output FET is electrically connected to a power supply node, and wherein the drain of the output FET is electrically connected to an output node, and
a current control stage electrically intermediate the power supply node and the drain of the source follower FET;

wherein the current limiter stage is configured to operate in a quiescent operating mode and an overload operating mode, such that
in the quiescent operating mode, the source follower FET and the output FET are configured to operate as a buffer stage that forms a closed feedback loop to feedback the output voltage of the voltage regulator circuit to an input of the amplifier stage, and
in the overload operating mode, the source follower FET is configured to act as a triode switch that electrically connects the current control stage to the gate of the output FET such that a current mirror forms between the current control stage and the output FET so that an output current of the voltage regulator circuit is clamped to a designated current controlled by the current control stage.

14. The voltage regulator circuit of claim 13 , wherein the current limiter stage further includes:
a source follower replica FET, wherein a source of the source follower replica FET is electrically connected to the current control stage, wherein a drain of the source follower replica FET is electrically connected to the drain of the source follower FET, and wherein the source follower replica FET is configured such that a drain-to-source voltage of the source follower replica FET is equal to a drain-to-source voltage of the source follower FET in the overload operating mode.

15. The voltage regulator circuit of claim 13 , wherein the current limiter stage further includes:
a first current source electrically connected to the power supply node and electrically intermediate the power supply node and the source of the source follower FET and the gate of the output FET.

16. The voltage regulator circuit of claim 13 , wherein the current limiter stage further includes:
a second current source electrically connected to the drain of the source follower FET.

17. The voltage regulator circuit of cl

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Dyer Kenneth Colin

Classifications

• G05F3/262

  using field-effect transistors only · CPC title

• G05F1/461

  using an operational amplifier as final control device · CPC title

• G05F1/445

  being transistors in series with the load · CPC title

• G05F1/573 Primary

  with overcurrent detector · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title