Ultrasound apparatuses and methods for fabricating ultrasound devices

Patent metadata

Field	Value
Publication number	US-11375980-B2
Application number	US-201916404672-A
Country	US
Kind code	B2
Filing date	May 6, 2019
Priority date	Nov 15, 2017
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

First claim

What is claimed is:

1. An ultrasound device, comprising:
a plurality of capacitive micromachined ultrasonic transducers (CMUT);
a first application-specific integrated circuit (ASIC) comprising a pulser configured to provide a signal to a CMUT of the plurality of CMUTs, integrated analog processing receive circuitry configured to process a signal produced by the CMUT in response to receiving an acoustic signal, an analog-to-digital converter (ADC) configured to digitize a signal provided by the analog processing receive circuitry, and serial-deserialized (SERDES) transmit circuitry, wherein the first ASIC is configured to operate at a first operating voltage in a range of approximately 30-80 Volts;
a second ASIC comprising SERDES receive circuitry and integrated digital processing circuitry configured to digitally process a signal provided by the SERDES receive circuitry, wherein the integrated digital processing circuitry is configured to operate at a second operating voltage in a range of approximately 0.45-0.9 Volts; and
a SERDES communication link coupling the SERDES transmit circuitry of the first ASIC and the SERDES receive circuitry of the second ASIC.

2. The ultrasound device of claim 1 , wherein the SERDES communication link comprises a through-silicon via (TSV).

3. The ultrasound device of claim 1 , wherein the first ASIC is implemented in a first technology node, the second ASIC is implemented in a second technology node, and the first technology node is different than the second technology node.

4. The ultrasound device of claim 3 , wherein the second technology node is a smaller technology node than the first technology node.

5. The ultrasound device of claim 3 , wherein the first technology node is 65 nm, 80 nm, 90 nm, 110 nm, 130 nm, 150 nm, 180 nm, 220 nm, 240 nm, 250 nm, 280 nm, 350 nm, or 500 nm.

6. The ultrasound device of claim 3 , wherein the second technology node is 90 nm, 80 nm, 65 nm, 55 nm, 45 nm, 40 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, or 3 nm.

7. The ultrasound device of claim 1 , wherein:
the SERDES communication link has a data rate of approximately 2-5 gigabits/second.

8. The ultrasound device of claim 1 , wherein the SERDES communication link is a first SERDES communication link, and wherein the ultrasound device comprises multiple SERDES communication links operating in parallel and coupling the SERDES transmit circuitry of the first ASIC and the SERDES receive circuitry of the second ASIC.

9. The ultrasound device of claim 1 , wherein:
the analog-to-digital converter (ADC) is one of multiple ADCs; and
the SERDES transmit circuitry is configured to receive data from the multiple ADCs in a multiplexed fashion.

10. The ultrasound device of claim 1 , wherein the ADC of the first ASIC is disposed electrically between the integrated analog processing receive circuitry and the SERDES transmit circuitry of the first ASIC.

11. The ultrasound device of claim 10 , further comprising a printed circuit board (PCB), wherein:
the SERDES communication link comprises a trace of the PCB, and the SERDES receive circuitry of the second ASIC is disposed between the trace of the PCB and the integrated digital processing circuitry of the second ASIC.

12. The ultrasound device of claim 1 , further comprising a printed circuit board (PCB), wherein:
the SERDES communication link comprises a trace of the PCB, and
the SERDES receive circuitry of the second ASIC is disposed between the trace of the PCB and the integrated digital processing circuitry of the second ASIC.

13. The ultrasound device of claim 1 , further comprising a printed circuit board (PCB), wherein the first and second ASICs are both coupled to the PCB.

14. The ultrasound device of claim 1 , wherein the first ASIC is disposed electrically between the plurality of CMUTs and the second ASIC.

Assignees

• Bfly Operations Inc

Inventors

• Chen Kailiang
• Sanchez Nevada J
• Alie Susan A
• Ralston Tyler S
• Rothberg Jonathan M
• Fife Keith G
• Lutsky Joseph

Classifications

• H04B11/00

  Transmission systems employing ultrasonic, sonic or infrasonic waves · CPC title

• A61B8/4483 Primary

  characterised by features of the ultrasound transducer · CPC title

• A61B8/54

  Control of the diagnostic device · CPC title

• A61B8/56

  Details of data transmission or power supply · CPC title

• G01S7/52017

  particularly adapted to short-range imaging (G01S7/53 takes precedence) · CPC title