Interleaving ADC error correction methods for Ethernet PHY

Patent metadata

Field	Value
Publication number	US-11374601-B2
Application number	US-202117200426-A
Country	US
Kind code	B2
Filing date	Mar 12, 2021
Priority date	Mar 13, 2020
Publication date	Jun 28, 2022
Grant date	Jun 28, 2022

Abstract

A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

First claim

What is claimed is:

1. A receiver circuit, comprising:
an interleaved analog-to-digital converter (ADC) including:
a first ADC having a clock input; and
a second ADC having a clock input and coupled in parallel with the first ADC;

a first delay circuit including:
a clock input adapted to be coupled to a clock source;
a control input; and
a clock output coupled to the clock input of the first ADC;

a second delay circuit including:
a clock input adapted to be coupled to the clock source;
a control input; and
a clock output coupled to the clock input of the second ADC;

a first-in-first-out (FIFO) memory coupled to the interleaved ADC;
a processing channel coupled to the FIFO memory, and including:
a slicer having an output;

an interleaving ADC timing error detector circuit including:
an input coupled to the output of the slicer;
a first output coupled to the control input of the first delay circuit; and
a second output coupled to the control input of the second delay circuit.

2. The receiver circuit of claim 1 , wherein:
the processing channel is a first processing channel;
the slicer is a first slicer;
the input of the interleaving ADC timing error detector circuit is a first input; and
the receiver circuit includes:
a second processing channel coupled to the FIFO memory, and including:
a second slicer having an input and an output; and

the interleaving ADC timing error detector circuit includes:
a second input coupled to the input or the output of the second slicer.

3. The receiver circuit of claim 2 , further comprising:
a first decision feedback equalizer (DFE) tap including:
an input coupled to the output of the first slicer; and
an output coupled to the first input of the timing error detector; and

a second DFE tap including:
an input coupled to the output of the second slicer; and
an output coupled to the second input of the interleaving ADC timing error detector circuit.

4. The receiver circuit of claim 2 , wherein:
the first slicer has an input;
the receiver circuit includes:
an ADC gain control circuit including:
a first input coupled to the output of the first slicer;
a second input coupled to the output of the second slicer;
a third input coupled to the input of the first slicer;
a fourth input coupled to the input of the second slicer; and
an output; and

the second processing channel includes:
a multiplier circuit including:
a first input coupled to the FIFO memory;
a second input coupled to the output of the ADC gain control circuit; and
an output.

5. A receiver circuit, comprising:
an interleaved analog-to-digital converter (ADC) including:
a first ADC; and
a second ADC in parallel with the first ADC;

a first delay circuit configured to delay a first clock signal provided to the first ADC;
a second delay circuit configured to delay a second clock signal provided to the second ADC;
a first processing channel configured to process data samples provided by the first ADC, and including a first slicer;
a second processing channel configured to process data samples provided by the second ADC, and including a second slicer; and
an interleaving ADC timing error detector circuit configured to control a first delay of the first delay circuit and a second delay of the second delay circuit responsive to an output signal of the first slicer and either an output signal or an input signal of the second slicer.

6. The receiver circuit of claim 5 , wherein the interleaving ADC timing error detector circuit is configured to generate an interleaving ADC timing error value as a correlation of the output signal of the first slicer and the input signal of the second slicer.

7. The receiver circuit of claim 6 , further comprising a decision feedback equalizer configured to reduce only inter-symbol interference present in the first processing channel.

8. The receiver circuit of claim 5 , further comprising:
a decision feedback equalizer including:
a first ADC first tap circuit configured to reduce inter-symbol interference in the first processing channel; and
a second ADC first tap circuit configured to reduce inter-symbol interference in the second processing channel;

wherein the interleaving ADC timing error detector circuit is configured to control the first delay circuit and the second delay circuit based on output of the first ADC first tap circuit and output of the second ADC first tap circuit.

9. The receiver circuit of claim 8 , wherein the interleaving ADC timing error detector circuit is configured to generate an interleaving ADC timing error value as a difference of the output of the first ADC first tap circuit and the output of the second ADC first tap circuit.

10. The receiver circuit of claim 8 , wherein:
the output of the first ADC first tap circuit represents inter-symbol interference in the first processing channel; and
the output of the second ADC first tap circuit represents inter-symbol interference in the second processing channel.

11. The receiver circuit of claim 8 , wherein the decision feedback equalizer includes N taps and taps 2-N are applied to reduce ISI in the first processing channel and the second processing channel.

12. The receiver circuit of claim 5 , further comprising:
an ADC gain control circuit configured to adjust an amplitude of data samples provided by the second ADC based on input of the first slicer, output of the first slicer, input of the second slicer, and output of the second slicer.

13. The receiver circuit of claim 12 , wherein the second processing channel includes a multiplier circuit configured to adjust the amplitude of the data samples provided by the second ADC based on a multiplier value provided by the ADC gain control circuit.

14. The receiver circuit of claim 12 , wherein the ADC gain control circuit is configured to generate a gain error value as a product of 1) the output of the first slicer, 2) the output of the second slicer, and 3) a difference of the input of the first slicer and the input of the second slicer.

15. A receiver circuit, comprising:
an analog front-end circuit, including:
an interleaved analog-to-digital converter (ADC) including:
a first ADC; and
a second ADC;

a digital signal processing circuit coupled to the analog front-end circuit, and including:
a first processing channel configured to process data samples provided by the first ADC, and including a first slicer;
a second processing channel configured to process data samples provided by the second ADC, and including a second slicer; and
an ADC gain control circuit configured to adjust an amplitude of data samples provided by the second ADC responsive to: input of the first slicer, output of the first slicer, input of the second slicer, and output of the second slicer.

16. The receiver circuit of claim 15 , wherein the ADC gain control circuit is configured to generate a gain error value as a product of 1) the output of the first slicer, 2) the output of the second slicer, and 3) a difference of the input of the first slicer and the input of the second slicer.

17. The receiver circuit of claim 15 , wherein the second processing channel includes a multiplier circuit configured to adjust the amplitude of the data samples provided by the second ADC based on a multiplier value provided by the ADC gain control circuit.

18. The receiver circuit of claim 15 , wherein:
analog front-end circuit includes:
a first delay circuit configured to delay a first clock signal provided to the first ADC;
a second delay ci

Assignees

• Texas Instruments Inc

Inventors

• Ganesan Raghu
• Radhakrishnan Saravanakkumar
• Rajai Kalpesh Laxmanbhai
• Roul Soumyajit
• Seth Sumantra

Classifications

• H03M1/0687

  using fault-tolerant coding, e.g. parity check, error correcting codes (H03M1/069 takes precedence) · CPC title

• H03M1/004

  Reconfigurable analogue/digital or digital/analogue converters (H03M1/02 takes precedence) · CPC title

• H04B1/1607

  Supply circuits (converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46) · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title