Integration circuit and control method and apparatus

Patent metadata

Field	Value
Publication number	US-11374492-B2
Application number	US-202016830939-A
Country	US
Kind code	B2
Filing date	Mar 26, 2020
Priority date	Jul 19, 2019
Publication date	Jun 28, 2022
Grant date	Jun 28, 2022

Abstract

An integration circuit is provided. The integration circuit includes a current source, a capacitor connected in series with the current source, a voltage source bias connected in series with the capacitor, a switch configured to connect a first node between the current source and the capacitor and a second node between the capacitor and the voltage source bias; and a switch control logic unit configured to control an on/off operation of the switch, wherein an integration operation is performed by the current source and the capacitor.

First claim

What is claimed is:

1. An integration circuit comprising:
a current source configured to supply a variable current based on a difference between a reference voltage V REF and a current sensing voltage V CS that increases for a predetermined time;
a capacitor connected in series with the current source;
a voltage source bias connected in series with the capacitor;
a switch configured to connect a first node between the current source and the capacitor and a second node between the capacitor and the voltage source bias; and
a switch control logic unit configured to control an on/off operation of the switch, wherein an integral operation is performed by the current source and the capacitor by supplying the variable current to the capacitor when the switch is turned off,
wherein when a transfer conductance value of the current source is gm, the variable current has a value of gm*(V REF −V CS ).

2. The circuit of claim 1 , wherein the switch control logic unit comprises an inversion buffer and an AND gate, and wherein the integration circuit is configured to be in a non-operational state when an output of the AND gate is at a high level and the integration circuit is configured to be in an operational state when the output of the AND gate is at a low level.

3. The circuit of claim 1 , wherein the second node of the voltage source bias is configured to maintain a constant value based on the voltage source bias.

4. The circuit of claim 1 , wherein an integral value obtained at the first node from the integral operation appears in a semicircular shape that is symmetrical with respect to a time at which the reference voltage V REF and the current sensing voltage V CS are equal.

5. The circuit of claim 3 , further comprising a comparator configured to compare a first integral value of the first node with a second integral value of the second node based on the integral operation.

6. The circuit of claim 1 , wherein a turn-on time of the switch does not change even when a transfer conductance value (gm) of the current source is changed or when a size of the capacitor is changed.

7. The circuit of claim 1 , wherein an operating time of the integration circuit does not change even when a transfer conductance value (gm) of the current source or a size of the capacitor is changed.

8. A control method of an integration circuit comprising a current source, a capacitor connected in series with the current source, a voltage source bias maintaining a constant value and connected in series with the capacitor, a switch configured to connect a first node between the current source and the capacitor and a second node between the capacitor and the voltage source bias, and a switch control logic unit configured to control an on/off operation of the switch, the method comprising:
supplying, by the current source, a variable current based on a difference between a reference voltage V REF that remains constant and a current sensing voltage V CS that increases for a predetermined time, to the capacitor to perform an integral operation;
performing a turn-on operation of the switch when an integral value of the integral operation and the voltage source bias are equal; and
performing a turn-off operation of the switch when the integral value of the integral operation and the voltage source bias are not equal,
wherein the switch is turned on to stop the integral operation, and the switch is turned off to start the integral operation.

9. The method of claim 8 , wherein an increase and a decrease in the integral value are the same for a time when the reference voltage V REF and the current sensing voltage V CS are the same.

10. The method of claim 8 , wherein a time at which the switch is turned on does not change even when a transfer conductance value (gm) of the current source is changed.

11. The method of claim 8 , wherein a time at which the switch is turned on does not change even when a size of the capacitor is changed.

12. The method of claim 8 , wherein an operating time of the integration circuit is constant when a transfer conductance value (gm) of the current source is changed, or a size of the capacitor is changed.

13. A switch controller comprising:
an integration circuit comprising a current source, a capacitor connected in series with the current source, a voltage source bias connected in series with the capacitor, a switch configured to connect a first node between the current source and the capacitor with a second node between the capacitor and the voltage source bias, and a switch control logic unit comprising an inversion buffer and an AND gate connected in series and configured to control an on/off operation of the switch;
a comparator configured to compare a first integral value of the first node with a second integral value of the second node based on an integral operation of the integration circuit, and output a switch-off signal SW_OFF to the switch control logic unit;
an off-time controller configured to count an off-time based on an output of the comparator; and
a switch driver configured to control an operation of a current control switch based on the output of the comparator and the off-time controller,
wherein the current source is configured to supply a variable current based on a difference between a reference voltage V REF and a current sensing voltage V CS that increases for a predetermined time, and
wherein the integral operation is performed by the current source and the capacitor by supplying the variable current to the capacitor when the switch is turned off.

14. The switch controller of claim 13 , wherein the integration circuit is configured to operate based on an output signal of the off-time controller.

15. The switch controller of claim 13 , wherein the off-time controller is configured to output a logic signal, which has a predetermined level, to a set terminal of the switch driver after a predetermined time is counted based on an output signal of the comparator.

16. An integration circuit comprising:
a single current source configured to supply a variable current based on a difference between a reference voltage V REF and a current sensing voltage V CS that increases for a predetermined time;
a voltage source bias;
a single capacitor connected in series with the single current source, and configured to perform an integral operation with the single current source;
a switch configured to connect a first node between the single current source and the single capacitor with a second node between the single capacitor and the voltage source bias; and
a switch control logic unit comprising an inversion buffer and an AND gate connected in series and configured to control on/off operations of the switch,
wherein the integral operation is performed by the single current source and the single capacitor by supplying the variable current to the single capacitor when the switch is turned off.

17. The circuit of claim 16 , further comprising a comparator connected to the first node and the second node, and configured to compare a first integral value of the first node with a second integral value of the second node based on the integral operation of the integration circuit, and output a switch-off signal SW_OFF to the AND gate of the switch control logic unit.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Lee Jang Hyuck
• Yoon Joo Han
• An Byoung Kwon
• Lee Jay

Classifications

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H03F2203/45026

  One or more current sources are added to the amplifying transistors in the differential amplifier · CPC title

• H03F2203/45541

  the IC comprising dynamic biasing means, i.e. controlled by the input signal · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title