Optoelectronic semiconductor chip

Patent metadata

Field	Value
Publication number	US-11374152-B2
Application number	US-201917054488-A
Country	US
Kind code	B2
Filing date	May 3, 2019
Priority date	May 11, 2018
Publication date	Jun 28, 2022
Grant date	Jun 28, 2022

Abstract

Provided is an optoelectronic semiconductor chip including a semiconductor layer sequence in which an active zone for generating radiation is located between a first semiconductor region and a second semiconductor region. A first electrical contact of the semiconductor layer sequence is applied to the first semiconductor region. A second electrical contact is applied to the second semiconductor region. The second electrical contact is located in a trench of the second semiconductor region. The trench is restricted to the second semiconductor region and ends at a distance from the active zone. A distance between a bottom of the trench and the active zone is at most 3 μm.

First claim

The invention claimed is:

1. An optoelectronic semiconductor chip comprising:
a semiconductor layer sequence in which an active zone for generating radiation is located between a first semiconductor region and a second semiconductor region,
a first electrical contact of the semiconductor layer sequence at the first semiconductor region, and
a second electrical contact of the semiconductor layer sequence at the second semiconductor region,
where
the second electrical contact is at least partially located in a trench of the second semiconductor region and touches the second semiconductor region in the trench,
a radiation is coupled out from the semiconductor layer sequence at least predominantly at the second semiconductor region, and
the trench is restricted to the second semiconductor region and terminates at a distance from the active zone, so that a distance (D) between a bottom of the trench and the active zone is at most 3 μm and, in addition, at least one of the following two possibilities is fulfilled, according to which:
at least one recess is formed in the first semiconductor region, so that the first semiconductor region is partially removed and the recess is spaced from the active zone and is opposite the trench, so that, seen in top view, the recess and the trench overlap one another and so that the recess ( 5 ) reduces or prevents the active zone in the region of the trench from being supplied with current from the first semiconductor region, and/or
the first contact covers the first semiconductor region in an areal manner, so that the first contact lies exclusively next to the second contact when the second semiconductor region is viewed in a top view, and a distance between the first and second contacting is at most 50% of an average width of the second contacting when viewed in a top view.

2. The optoelectronic semiconductor chip according to claim 1 ,
in which side walls of the trench are free of the second electrical contact,
wherein a center angle (A) between an underside of the second electrical contact and a radiation generating portion of the active zone is between 1 mrad and 80 mrad inclusive.

3. The optoelectronic semiconductor chip according to claim 1 ,
in which the second electrical contact, as viewed in at least one cross-section perpendicular to the trench, lies completely in the associated trench,
wherein a ratio of a length of the second electrical contact and a width of the second electrical contact is at least 15 when viewed in top view.

4. The optoelectronic semiconductor chip according to claim 1 ,
in which the second electrical contact projects beyond the associated trench in a direction away from the bottom as viewed in at least one cross-section perpendicular to the trench,
wherein the bottom is predominantly directly covered by the second electrical contact.

5. The optoelectronic semiconductor chip according to claim 1 ,
in which the recess is wider than the associated trench, projects beyond the trench on both sides as seen in cross-section and reaches closer to the active zone than the trench.

6. The optoelectronic semiconductor chip according to claim 1 ,
in which the side walls of the trench are at least partially provided with a mirror layer,
wherein the mirror layer is electrically insulating and covers the bottom of the trench to a maximum of 40%.

7. The optoelectronic semiconductor chip according to claim 1 ,
in which the side walls of the trench are at least partially provided with an anti-reflection layer and/or with a roughening,
wherein the bottom of the trench is free of the anti-reflection layer and/or the roughening.

8. The optoelectronic semiconductor chip according to claim 1 ,
in which the side walls of the trench are inclined inwards, so that in top view the bottom of the trench is partially covered by the side walls.

9. The optoelectronic semiconductor chip according to claim 1 ,
in which the second electrical contact is trapezoidal when viewed in cross-section, so that a width of the second electrical contact continuously decreases in the direction away from the bottom of the trench.

10. The optoelectronic semiconductor chip according to claim 1 ,
in which the second electrical contact is configured for current distribution in a direction parallel to the active zone, so that, seen in top view, a branched structure is formed across the semiconductor layer sequence by the second electrical contact,
wherein the first electrical contact is formed with a plurality of point-like current supply regions to the first semiconductor region, so that the first electrical contact contacts the first semiconductor region only to an area proportion of at most 40%.

11. The optoelectronic semiconductor chip according to claim 1 ,
in which the active zone extends continuously over the semiconductor layer sequence, so that the active zone runs continuously under the at least one trench.

12. The optoelectronic semiconductor chip according to claim 1 ,
in which the second semiconductor region comprises an etch stop layer and the trench terminates at or below the etch stop layer,
wherein either the etch stop layer is of a phosphide and the second semiconductor region is of an arsenide or an arsenide having a high aluminum content, or the etch stop layer is of an arsenide and the second semiconductor region is of a phosphide.

13. The optoelectronic semiconductor chip according to claim 1 ,
in which the second electrical contact is a metallic contact and consists of one or more metals,
wherein, starting from the second electrical contact, alloying is carried out into the semiconductor layer sequence, and
wherein the alloying terminates spaced from the active zone.

14. The optoelectronic semiconductor chip according to claim 1 ,
in which a plurality of the trenches run parallel to one another and the trenches are each provided with the second electrical contact,
where, viewed in top view, the average distance between adjacent trenches is between 30 μm and 200 μm inclusive.

15. The optoelectronic semiconductor chip according to claim 1 ,
in which the bottom has a width between 2 μm and 20 μm inclusive and in which at least one trench has a depth between 1.5 μm and 8 μm inclusive,
wherein a thickness of the second semiconductor region is between 2 μm and 11 μm inclusive, and
wherein the semiconductor layer sequence is based on the material system AlInGaAsP.

16. The optoelectronic semiconductor chip according to claim 1 ,
in which the second semiconductor region on an upper side facing away from the active zone is free, apart from the second electrical contact, from electrically conductive materials such as transparent conductive oxides or radiation-transmitting metal layers,
wherein the first semiconductor region is p-doped and the second semiconductor region ( 22 ) is n-doped.

17. An optoelectronic semiconductor chip comprising:
a semiconductor layer sequence in which an active zone for generating radiation is located between a first semiconductor region and a second semiconductor region,
a first electrical contact of the semiconductor layer sequence at the first semiconductor region, and
a second electrical contact of the semiconductor layer sequence at the second semiconductor region,
wherein
the second electrical contact is at least partially located in a trench of the second semiconductor region and touches the second semiconductor region in the trench, wherein side walls of the trench are free from the second electrical contact,
a radiation is coupled out from the semicon

Assignees

• Osram Oled Gmbh

Inventors

• Heckelmann Stefan
• Rudolph Andreas
• Tonkikh Alexander

Classifications

• H10H20/841

  Reflective coatings, e.g. dielectric Bragg reflectors · CPC title

• H10H20/824

  comprising only Group III-V materials, e.g. GaP · CPC title

• H10H20/82

  Roughened surfaces, e.g. at the interface between epitaxial layers · CPC title

• H10H20/8312 Primary

  extending at least partially through the bodies · CPC title

• H10H20/831

  characterised by their shape · CPC title