Thin film transistor, manufacturing method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11374033-B2
Application number	US-201916710100-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Jan 31, 2019
Publication date	Jun 28, 2022
Grant date	Jun 28, 2022

Abstract

A thin film transistor, method of manufacturing the thin film transistor, an array substrate comprising the thin film transistor, and a display device comprising the array substrate. The thin film transistor comprises a substrate; a first electrode on the substrate; an active layer on a side of the first electrode away from the substrate; and a second electrode on a side of the active layer away from the first electrode. The first electrode and the second electrode are connected to the active layer, respectively. are also disclosed.

First claim

The invention claimed is:

1. A thin film transistor comprising:
a substrate, and
a buffer layer, an active layer and an insulating layer stacked on the substrate in sequence,
wherein the thin film transistor further comprises a source, a drain, a first via and a second via,
wherein the source is located between the active layer and the substrate, and the source is covered by the buffer layer, the drain is located on a surface of the insulating layer facing away from the substrate, so that the source and the drain are respectively located at two sides of the active layer directly opposite to each other,
wherein the first via is in the buffer layer and extends only between a surface of the source facing away from the substrate and a first surface of the active layer facing the substrate, and the second via is in the insulating layer and extends only between a second surface of the active layer facing away from the substrate and a surface of the drain facing the substrate, such that both the first via and the second via do not penetrate through the active layer, wherein the first surface of the active layer is directly opposite to the second surface of the active layer, and wherein the source comprises a light shielding material.

2. The thin film transistor according to claim 1 , wherein the active layer comprises a low temperature polysilicon material, and an orthographic projection of the source on the substrate at least partially overlaps an orthographic projection of the active layer on the substrate.

3. The thin film transistor according to claim 2 , wherein the orthographic projection of the active layer on the substrate has an area larger than an area of the orthographic projection of the source on the substrate.

4. The thin film transistor according to claim 1 , wherein the insulating layer comprises a gate insulating layer on a side of the active layer away from the buffer layer, and an interlayer insulating layer on a side of the gate insulating layer away from the active layer, the thin film transistor further comprises a gate between the interlayer insulating layer and the gate insulating layer.

5. The thin film transistor according to claim 1 , wherein both the first via and the second via comprise a conductive material, wherein the drain is in unity with the conductive material filling the second via.

6. The thin film transistor according to claim 4 , wherein an orthographic projection of the source on the substrate does not overlap an orthographic projection of the drain on the substrate, and
wherein an orthographic projection of the first via on the substrate, and an orthographic projection of the second via on the substrate do not overlap an orthographic projection of the gate on the substrate.

7. A method of manufacturing the thin film transistor according to claim 1 , comprising:
forming the source on the substrate;
forming the active layer on a side of the source away from the substrate; and
forming the drain on the side of the active layer away from the source.

8. The method according to claim 7 , further comprising:
forming the buffer layer covering the source on the substrate;
forming the first via in the buffer layer, the insulating layer and the active layer, the first via communicating the active layer with the source;
forming the insulating layer between the active layer and the drain; and
forming the second via in the insulating layer and the active layer, the second via communicating the drain and the active layer.

9. The method according to claim 7 , wherein the active layer is fabricated using a low temperature polysilicon material, the source is fabricated using a light shielding material, and an orthographic projection of the source on the substrate at least partially overlaps an orthographic projection of the active layer on the substrate.

10. The method according to claim 8 , wherein the drain and a conductive material filling the second via are simultaneously formed in a single patterning process.

11. The method according to claim 8 , wherein forming the insulating layer comprises forming a gate insulating layer on a side of the active layer away from the buffer layer, and forming an interlayer insulating layer on a side of the gate insulating layer away from the active layer, and the method further comprises:
forming a gate between the interlayer insulating layer and the gate insulating layer.

12. The method according to claim 11 , wherein an orthographic projection of the source on the substrate does not overlap an orthographic projection of the drain on the substrate, and
wherein an orthographic projection of the first via on the substrate, and an orthographic projection of the second via on the substrate do not overlap an orthographic projection of the gate on the substrate.

13. The method according to claim 12 , wherein the drain and a conductive material filling the first via and the second via are simultaneously formed in a single patterning process.

14. An array substrate comprising the thin film transistor according to claim 1 .

15. The array substrate according to claim 14 , further comprising a data line in a same layer as the drain.

16. The array substrate according to claim 14 , wherein the active layer comprises a low temperature polysilicon material, and an orthographic projection of the source on the substrate at least partially overlaps an orthographic projection of the active layer on the substrate.

17. The array substrate according to claim 16 , wherein the orthographic projection of the active layer on the substrate has an area larger than an area of the orthographic projection of the source on the substrate.

18. A display device comprising the array substrate according to claim 14 .

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Sun Xuefeng
• Liu Guoliang

Classifications

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title