Converter circuit, corresponding device and offset compensation method

Patent metadata

Field	Value
Publication number	US-11368165-B2
Application number	US-202117211355-A
Country	US
Kind code	B2
Filing date	Mar 24, 2021
Priority date	Apr 2, 2020
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.

First claim

What is claimed is:

1. A converter circuit, comprising:
an analog-to-digital signal conversion path from an input port to an output port, the input port configured to receive an analog input signal having an offset, and the output port configured to deliver a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog input signal;
a digital-to-analog feedback path from the output port to the input port, the feedback path comprising a digital-to-analog converter configured to apply to the input port of the analog-to-digital signal conversion path an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first states and second states during which the two-state signal has a first value and a second value, respectively; and
M-bit digital word generation circuitry sensitive to the two-state signal and configured to produce the M-bit digital word, alternately:
during the first states, as a first M-bit digital word which is a function of the digital output signal quantized over the M levels; and
during the second states, as a second M-bit digital word which is a function a correction value of the offset in the analog input signal.

2. The converter circuit of claim 1 , wherein the digital word generation circuitry comprises two-state signal generation circuitry configured to produce the two-state signal having the alternating first states and second states, wherein the two-state signal generation circuitry comprises:
a counter circuit configured to be clocked by a clock signal; and
a counter threshold circuit configured to set the two-state signal to the first state and to the second state at a first count value and a second count value, respectively, of the counter circuit.

3. The converter circuit of claim 2 , wherein the counter circuit comprises an N-bit counter, and the counter threshold circuit comprises N-bit thresholds, providing the first count value and the second count value, respectively.

4. The converter circuit of claim 1 , wherein the digital-to-analog converter in the digital-to-analog feedback path comprises a plurality of M bias cells, wherein each bias cell in the plurality of M bias cells is individually switchable, as a function of a logical value of a respective one of the bits in the M-bit digital word, to a conductive state during which the bias cell electrically couples at least one output line of the digital-to-analog converter to at least one signal source.

5. The converter circuit of claim 4 , wherein:
the input port to the analog-to-digital signal conversion path comprises a differential input with a first input node and a second input node configured to receive the analog input signal applied therebetween;
the digital-to-analog converter in the digital-to-analog feedback path comprises a first output line and a second output line configured to apply the analog feedback signal between the first input node and the second input node of the input port of the analog-to-digital signal conversion path; and
in the conductive state, each bias cell electrically couples the first output line and the second output line of the digital-to-analog converter to a first signal source and a second signal source, respectively.

6. The converter circuit of claim 4 , wherein the M-bit digital word generation circuitry comprises a dynamic matching circuit configured to receive the M-bit digital word and to cyclically vary the respective one of the bits in the M-bit digital word as a function of which each bias cell in the plurality of M bias cells is individually switchable to the conductive state.

7. The converter circuit of claim 4 , wherein:
the M bias cells are configured to provide respective, substantially identical bias contributions to the digital-to-analog converter;
at least one of the M bias cells comprises a set of H bias sub-cells, wherein each sub-cell in the set of H bias sub-cells is configured to provide a bias current contribution to the digital-to-analog converter which is 1/H the substantially identical bias contribution; and
the H bias sub-cells in the at least one of the M bias cells are configured to be switched to the conductive state:
identically to one another during the first states as a function of the logical value of the respective one of the bits in the M-bit digital word to provide a respective bias contribution of the at least one of the M bias cells to the digital-to-analog converter; and
differently from one another during the second states to provide a reduced bias contribution of the at least one of the M bias cells to the digital-to-analog converter, the reduced bias contribution being a function of a number of the sub-cells in the set of H bias sub-cells that are in the conductive state.

8. The converter circuit of claim 4 , wherein the digital-to-analog converter in the digital-to-analog feedback path comprises a set of L supplemental bias cells activatable during the second states, as a function of a third digital word, the third digital word comprising the second M-bit digital word supplemented by a set of L bits of correction value of the offset in the analog input signal.

9. The converter circuit of claim 4 , wherein each bias cell comprises an electronic switch.

10. The converter circuit of claim 9 , wherein each electronic switch comprises a metal-oxide-semiconductor field-effect transistor.

11. A device, comprising:
a signal source, the signal source configured to produce an analog signal having an offset; and
a converter circuit comprising:
an analog-to-digital signal conversion path from an input port to an output port, the input port coupled to the signal source to receive the analog signal having the offset, and the output port configured to deliver a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog signal from the signal source;
a digital-to-analog feedback path from the output port to the input port, the feedback path comprising a digital-to-analog converter configured to apply to the input port of the analog-to-digital signal conversion path an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first states and second states during which the two-state signal has a first value and a second value, respectively; and
M-bit digital word generation circuitry sensitive to the two-state signal and configured to produce the M-bit digital word, alternately:
during the first states, as a first M-bit digital word which is a function of the digital output signal quantized over the M levels; and
during the second states, as a second M-bit digital word which is a function a correction value of the offset in the analog signal.

12. The device according to claim 11 , further comprising:
a digital decimation filter coupled to the output port and configured to filter the digital output signal from the output port.

13. The device of claim 11 , wherein the device is integrated on a semiconductor substrate.

14. A method, comprising:
receiving, at an input port of an analog-to-digital signal conversion path, an analog input signal having an offset;
delivering, at an output port, a digital output signal quantized over M levels, the digital output signal resulting from conversion to digital of the analog input signal;
feeding back, from the output port to the input port, via a digital-to-analog feedback path comprising a digital-to-analog converter, an analog feedback signal produced as a function of a

Assignees

• St Microelectronics Srl

Inventors

• Ippolito Calogero Marco
• Vaiana Michele

Classifications

• H03M3/348

  using return-to-zero signals · CPC title

• H03M3/356 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M3/494) · CPC title

• H03M1/34 Primary

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/494 Primary

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title