Deglitch circuit for a differential-signal-detection circuit

Patent metadata

Field	Value
Publication number	US-11368145-B1
Application number	US-202117452413-A
Country	US
Kind code	B1
Filing date	Oct 27, 2021
Priority date	Oct 27, 2021
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

First claim

What is claimed is:

1. A differential-signal-detection circuit, comprising:
an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal;
a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal;
a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and
an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal;
wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

2. The circuit of claim 1 :
wherein the output stage is a digital circuit and the deglitch circuit is configured to prevent changes in the differential-signal-detection signal during the inter-symbol period of the differential input signal.

3. The circuit of claim 1 :
wherein the deglitch circuit is configured to generate a current; and
wherein the output stage includes a capacitive circuit configured to be charged by the current when both the first and second comparator output signals are below a first threshold signal level.

4. The circuit of claim 3 :
wherein the output stage includes an output configured to carry the differential-signal-detection signal;
wherein a deglitch voltage is defined between the capacitive circuit and the output; and
wherein the deglitch voltage is below a second threshold signal level during the inter-symbol period.

5. The circuit of claim 4 :
wherein when the deglitch voltage is below the second threshold signal level, then the differential-signal-detection signal is in a first state; and
wherein when the deglitch voltage is above the second threshold signal level, then the differential-signal-detection signal is in a second state.

6. The circuit of claim 3 :
wherein the deglitch circuit includes a set of transistors configured as a current mirror.

7. The circuit of claim 4 :
wherein the output stage includes a NOR gate configured to receive both the first and second comparator output signals and the current from the deglitch circuit.

8. The circuit of claim 7 :
wherein the NOR gate is configured to pass the current to the capacitive circuit when both the first and second comparator output signals are below the first threshold signal level.

9. The circuit of claim 3 :
wherein a deglitch voltage is defined between the capacitive circuit and the output; and
wherein the capacitor is configured to attenuate the deglitch voltage during the inter-symbol period of the differential input signal.

10. The circuit of claim 3 :
wherein the output stage includes a NOR gate configured to discharge the capacitive circuit when either of the first and second comparator output signals are above the first threshold signal level.

11. The circuit of claim 1 :
wherein the input stage includes a first transistor coupled to receive a first polarity of the differential input signal, and a second transistor coupled to receive a second polarity of the differential input signal;
wherein the input stage includes a first current source coupled to the first transistor a first input of each the first comparator and the second comparator; and
wherein the input stage includes a second current source coupled to the second transistor a second input of each the first comparator and the second comparator.

12. The circuit of claim 11 :
wherein the input stage includes a first resistance coupled between the first transistor and the first current source; and
wherein the input stage includes a second resistance coupled between the second transistor and the second current source.

13. The circuit of claim 12 :
wherein the first resistance and the second resistance are variable resistances.

14. The circuit of claim 13 :
wherein the first and second resistances are variable in response to a controller signal.

15. The circuit of claim 1 :
wherein the differential-signal-detection circuit is embedded in a squelch-detector; and
wherein a first state of the differential-signal-detection signal corresponds to an un-squelched state, and a second state of the differential-signal-detection signal corresponds to a squelched state.

16. The circuit of claim 1 :
wherein the differential-signal-detection circuit is embedded in a disconnect-detector; and
wherein a first state of the differential-signal-detection signal corresponds to a connected state, and a second state of the differential-signal-detection signal corresponds to a disconnected state.

17. The circuit of claim 1 :
wherein the differential-signal-detection circuit is embedded in a repeater-circuit; and
wherein the differential input signal is either an eUSB or USB signal.

Assignees

• Nxp Usa Inc

Inventors

• Liu Xiaoqun
• Delshadpour Siamak

Classifications

• H03K5/2472 Primary

  using field effect transistors (H03K5/2436 takes precedence) · CPC title

• H03K5/22

  Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00) · CPC title

• H03K5/1252 Primary

  Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) · CPC title

• H03K5/086

  generated by feedback · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title