Thin film transistor and fabricating method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11367791-B2
Application number	US-201816473456-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Jan 5, 2018
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

The present disclosure provides a thin film transistor, a fabricating method thereof, an array substrate, and a display device. The thin film transistor includes: a substrate; a channel region; a heavily doped first semiconductor pattern located on both sides of the channel region; a second semiconductor pattern disposed on the heavily doped first semiconductor pattern; a gate insulating layer covering the channel region and the second semiconductor pattern; a gate pattern disposed on the gate insulating layer, an orthographic projection of the gate pattern on the substrate being within an orthographic projection of the channel region on the substrate; and a source pattern and a drain pattern in contact with the heavily doped first semiconductor pattern through the first via and the second via, respectively.

First claim

We claim:

1. A thin film transistor comprising:
a heavily doped first semiconductor pattern on a substrate, having an opening;
a second semiconductor layer comprising an uncrystallized portion disposed on the heavily doped first semiconductor pattern and a crystallized portion filling the opening, the second semiconductor layer having a surface comprising a recess at the crystallized portion;
a gate insulating layer covering the second semiconductor layer;
a gate pattern disposed on the gate insulating layer, an orthographic projection of the gate pattern on the substrate being within an orthographic projection of the opening on the substrate, the gate pattern has a cross section of an inverted trapezoid including a lower base close to the gate insulating layer and an upper base away from the gate insulating layer, and the upper base is longer than the lower base;
a first via and a second via on two sides of the gate pattern, respectively, wherein the first via and the second via are disposed to penetrate, the gate insulating layer and the second semiconductor layer, and extend to the heavily doped first semiconductor pattern; and
a source pattern and a drain pattern in contact with the heavily doped first semiconductor pattern through the first via and the second via, respectively,
wherein the first semiconductor pattern includes dents, a depth of each of the dents is less than a thickness of the first semiconductor pattern, and the source pattern and the drain pattern fill the dents.

2. The thin film transistor of claim 1 , further comprising:
a buffer layer located between the heavily doped first semiconductor pattern and the substrate.

3. The thin film transistor of claim 1 , further comprising:
a dielectric layer covering the gate pattern, and
wherein the source pattern and the drain pattern are formed on the dielectric layer.

4. The thin film transistor of claim 1 , wherein a material of the heavily doped first semiconductor pattern comprises polysilicon, and a material of the uncrystallized portion comprises amorphous silicon.

5. The thin film transistor of claim 1 , wherein the opening has a length of 2-3 μm.

6. An array substrate comprising the thin film transistor of claim 1 .

7. A display device comprising the array substrate of claim 6 .

8. A fabricating method of a thin film transistor, comprising:
forming a heavily doped first semiconductor pattern on a substrate, having an opening;
forming a second semiconductor layer comprising uncrystallized second semiconductor pattern disposed on the heavily doped first semiconductor pattern and a crystallized portion filling the opening, the second semiconductor layer having a surface comprising a recess at the crystalized portion;
forming a gate insulating layer covering the second semiconductor pattern;
forming a gate pattern on the gate insulating layer, an orthographic projection of the gate pattern on the substrate being within an orthographic projection of the opening on the substrate, the gate pattern has a cross section of an inverted trapezoid including a lower base close to the gate insulating layer and an upper base away from the gate insulating layer, and the upper base is longer than the lower base;
forming a first via and a second via on two sides of the gate pattern, respectively, wherein the first via and the second via are disposed to penetrate, the gate insulating layer and the second semiconductor pattern, and extend to the heavily doped first semiconductor pattern;
forming a source pattern and a drain pattern, the source pattern and the drain pattern being in contact with the heavily doped first semiconductor pattern through the first via and the second via, respectively,
wherein the first semiconductor pattern includes dents, a depth of each of the dents is less than a thickness of the first semiconductor pattern, and the source pattern and the drain pattern fill the dents.

9. The fabricating method of claim 8 , wherein said forming the heavily doped first semiconductor pattern, and said forming the second semiconductor pattern comprise:
forming a first semiconductor layer on the substrate;
heavily doping the first semiconductor layer;
forming the opening at a predetermined location of the first semiconductor layer to form the heavily doped first semiconductor pattern;
forming the second semiconductor layer on the heavily doped first semiconductor pattern, wherein the second semiconductor layer covers the opening;
crystallizing a portion of the second semiconductor layer located at the opening; and forming the second semiconductor pattern by an uncrystallized portion of the second semiconductor layer.

10. The fabricating method of claim 8 , wherein said forming the heavily doped first semiconductor pattern, and said forming the second semiconductor pattern comprise:
forming a first semiconductor layer on the substrate;
forming the opening at a predetermined location of the first semiconductor layer to form a first semiconductor pattern;
heavily doping the first semiconductor pattern to form the heavily doped first semiconductor pattern;
forming a second semiconductor layer on the heavily doped first semiconductor pattern, wherein the second semiconductor layer covers the opening;
crystallizing a portion of the second semiconductor layer located at the opening, and forming the second semiconductor pattern by an uncrystallized portion of the second semiconductor layer.

11. The fabricating method of claim 9 , wherein before said forming the first semiconductor layer on the substrate, the fabricating method further comprises:
forming a buffer layer on the substrate.

12. The fabricating method of claim 8 , wherein before said forming the first via and the second via on two sides of the gate pattern, respectively, the fabricating method further comprises:
forming a dielectric layer covering the gate pattern,
wherein said forming a source pattern and a drain pattern comprises: forming the source pattern and the drain pattern on the dielectric layer.

13. The fabricating method of claim 8 , wherein a material of the heavily doped first semiconductor pattern comprises polysilicon, a material of the second semiconductor pattern comprises amorphous silicon.

14. The fabricating method of claim 8 , wherein the opening has a length of 2-3 μm.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Qiang Zhaohui
• Du Jianhua
• Guan Feng
• Li Chunhao

Classifications

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6713 Primary

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D86/425

  having different crystal properties in different TFTs or within an individual TFT · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title