Multi-chip package structure having dummy pad disposed between input/output units

Patent metadata

Field	Value
Publication number	US-11367710-B2
Application number	US-202017034161-A
Country	US
Kind code	B2
Filing date	Sep 28, 2020
Priority date	Jul 24, 2020
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

First claim

What is claimed is:

1. A multi-chip package structure, comprising:
a package carrier comprising a chip bonding area disposed on a central part thereof, and a plurality of outer leads disposed on at least one side thereof and configured to be electrically connected to an external preset electronic circuit; and
at least two chips comprising a first chip and a second chip, wherein the first chip is fixed on the chip bonding area of the package carrier and comprises an core disposed therein, and a plurality of input/output units and a plurality of first bonding pads disposed in an outward order from at least one side of the core and electrically connected to the core, and each of the plurality of first bonding pads is electrically connected to the corresponding one of the plurality of outer leads through a first wire, and the first chip further comprises a plurality of dummy pads disposed thereon, and each of the plurality of dummy pads is disposed between one of the plurality of input/output units and the at least one side of the core;
wherein the second chip is stacked and fixed on a top of the core of the first chip, and comprises at least one group of second bonding pads electrically connected to the corresponding ones of the plurality of outer leads through a plurality of second wires and the plurality of dummy pads.

2. The multi-chip package structure according to claim 1 , wherein the first chip comprises a transistor layer, a plurality of metal layers, and a plurality of VIA layers, and each of the metal layer comprises a routing line disposed in a direction of X axis or Y axis, and each of the plurality of VIA layers is disposed between the two longitudinally-adjacent of the plurality of metal layers and comprises a conductive via configured to connect the routing lines of the two longitudinally-adjacent of the plurality of metal layers, the core of the first chip is electrically connected to the plurality of input/output units and the plurality of first bonding pads, in a sequential order, through the preset routing lines of the plurality of metal layers.

3. The multi-chip package structure according to claim 2 , wherein the plurality of dummy pads are disposed between the core and the ones of the plurality of input/output units disposed in two different and adjacent arrangement directions, respectively, and the uppermost two of the plurality of metal layers comprises routing lines configured to electrically connect the plurality of dummy pads disposed in two different and adjacent arrangement directions.

4. The multi-chip package structure according to claim 1 , wherein the first chip comprises a seal ring disposed between the core and the plurality of first bonding pads, and the plurality of input/output units are disposed on the seal ring.

5. The multi-chip package structure according to claim 4 , wherein the plurality of first bonding pads and a plurality of dummy pads disposed on two relative outer sides of one of the plurality of input/output units on at least one side of the first chip are in an alignment arrangement.

6. The multi-chip package structure according to claim 4 , wherein the plurality of first bonding pads and the plurality of dummy pads disposed on two relative outer sides of one of the plurality of input/output units on at least one side of the first chip are in a misalignment arrangement.

7. The multi-chip package structure according to claim 1 , wherein each of the second bonding pads in the at least one group of second bonding pads of the second chip is electrically connected to the corresponding one of the plurality of dummy pad and the corresponding one of the plurality of outer leads through the same one of the plurality of second wires.

8. The multi-chip package structure according to claim 1 , wherein each of the plurality of second bonding pads in the at least one group of second bonding pads of the second chip is electrically connected to corresponding one of the plurality of dummy pads on the surface of the first chip through one of the plurality of second wires, and the another one of the plurality of dummy pads is electrically connected to the corresponding one of the plurality of outer leads through another one of the plurality of second wires.

9. The multi-chip package structure according to claim 1 , wherein the second chip is a memory chip, an application processor chip, or a graphics processing unit.

Assignees

• Egalax_Empia Tech Inc

Inventors

• Lin Po-Chuan

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title