Semiconductor device with through-substrate via
US-2021175153-A1 · Jun 10, 2021 · US
Semiconductor device with through-substrate via
US11367672B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11367672-B2 |
| Application number | US-201917052452-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 20, 2019 |
| Priority date | May 3, 2018 |
| Publication date | Jun 21, 2022 |
| Grant date | Jun 21, 2022 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.5 times the lateral extent of the via in the lateral direction, and the lateral extent of the contact layer is smaller than the lateral extent of the via or the lateral extent of the contact layer amounts to at least 2.5 times the lateral extent of the via.
First claim
Opening claim text (preview).
We claim: 1. A semiconductor device, comprising: a semiconductor body; an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side; an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via; and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction, wherein: the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction and is electrically connected with the contact layer by at least one electrically conductive connection, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.5 times the lateral extent of the via in the lateral direction, and the lateral extent in the lateral direction of the contact layer is smaller than the lateral extent of the via in the lateral direction. 2. The semiconductor device according to claim 1 , wherein the etch-stop layer is arranged symmetrically with respect to the via. 3. The semiconductor device according to claim 1 , wherein the contact layer is arranged symmetrically with respect to the via. 4. The semiconductor device according to claim 1 , wherein at least one further contact layer is arranged at the bottom side of the via in a plane which is parallel to the lateral direction. 5. The semiconductor device according to claim 4 , wherein the lateral extent of the further contact layer is smaller than the lateral extent of the via or the lateral extent of the further contact layer amounts to at least 2.5 times the lateral extent of the via. 6. The semiconductor device according to claim 1 , wherein the etch-stop layer comprises copper and/or aluminum. 7. The semiconductor device according to claim 1 , wherein the contact layer comprises copper and/or aluminum. 8. The semiconductor device according to claim 1 , wherein at least one of the etch-stop layer and the contact layer is electrically connected with an integrated circuit of the semiconductor device. 9. The semiconductor device according to claim 1 , wherein at least one of the at least one contact layer is a structured layer which is structured with an electrically non-conductive material in such a way that it is formed as a grid. 10. The semiconductor device according to claim 1 , wherein the lateral extent of the etch-stop layer and the lateral extent of the contact layer reduces the probability for the formation of cracks within or around the via. 11. The semiconductor device according to claim 1 , wherein the etch-stop layer and the contact layer contact a single via. 12. The semiconductor device according to claim 1 , wherein the lateral extent of the contact layer amounts to at least 5 times the lateral extent of the via.
Assignees
Inventors
Classifications
comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title
Structures or relative sizes of bond pads · CPC title
the principal metal being copper · CPC title
the principal metal being aluminium · CPC title
Vias, e.g. via plugs · CPC title
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Frequently asked questions
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- What does patent US11367672B2 cover?
- A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral directio…
- Who is the assignee on this patent?
- Ams Ag
- What technology area does this patent fall under?
- Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 21 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).