Precision structured glass articles, integrated circuit packages, optical devices, microfluidic devices, and methods for making the same

Patent metadata

Field	Value
Publication number	US-11367665-B2
Application number	US-201816633368-A
Country	US
Kind code	B2
Filing date	Jul 24, 2018
Priority date	Jul 24, 2017
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

The present disclosure relates to a reconstituted wafer- and/or panel-level package comprising a glass substrate having a plurality of cavities. Each cavity is configured to hold a single IC chip. The reconstituted wafer- and/or panel-level package can be used in a fan-out wafer or panel level packaging process. The glass substrate can include at least two layers having different photosensitivities with one layer being sufficiently photosensitive to be capable of being photomachined to form the cavities.

First claim

The invention claimed is:

1. A packaged integrated circuit comprising:
a structured glass article comprising a glass cladding layer fused to a glass base layer and a cavity formed in the glass cladding layer, wherein the glass base layer defines a floor of the cavity and the glass cladding layer defines sidewalls of the cavity; and
an integrated circuit chip disposed within the cavity;
wherein a width of the cavity is no more than 20 μm larger than a width of the integrated circuit chip; and
wherein a length of the cavity is no more than 20 μm larger than a length of the integrated circuit chip.

2. The packaged integrated circuit of claim 1 , wherein a depth of the cavity is no more than 20 μm larger than a thickness of the integrated circuit chip.

3. The packaged integrated circuit of claim 1 , wherein a depth of the cavity is about 5% to about 90% of a thickness of the integrated circuit chip.

4. The packaged integrated circuit of claim 3 , comprising a planarizing layer disposed on the structured glass article adjacent the integrated circuit chip.

5. The packaged integrated circuit of claim 1 , wherein the packaged integrated circuit is free of resin molding compound disposed within the cavity.

6. The packaged integrated circuit of claim 1 , wherein a difference between a first depth of the cavity at a first position along the perimeter of the cavity and a second depth of the cavity at a second position along the perimeter of the cavity opposite the first position is at most about 5 μm.

7. The packaged integrated circuit of claim 1 , comprising a redistribution layer disposed on the integrated circuit chip.

8. The packaged integrated circuit of claim 7 , comprising a ball grid array disposed on the redistribution layer.

9. The packaged integrated circuit of claim 1 , wherein:
the glass cladding layer comprises a first glass cladding layer fused to a first side of the glass base layer and a second glass cladding layer fused to a second side of the glass base layer opposite the first glass cladding layer;
the cavity comprises a first cavity formed in the first glass cladding layer and a second cavity formed in the second glass cladding layer; and
the integrated circuit chip comprises a first integrated circuit chip disposed within the first cavity and a second integrated circuit chip disposed within the second cavity.

10. The packaged integrated circuit of claim 9 , wherein the glass base layer is non-transmissive to radiation useful to expose at least one of the first glass cladding layer or the second glass cladding layer to form the cavity therein.

11. A wafer- or panel-level package comprising the packaged integrated circuit of claim 1 , wherein:
the cavity comprises a plurality of cavities; and
the integrated circuit chip comprises a plurality of integrated circuit chips each disposed within one of the plurality of cavities.

12. A structured glass article comprising:
a glass substrate comprising a glass cladding layer fused to a glass base layer; and
one or more cavities formed in the glass cladding layer of the glass substrate;
wherein the glass base layer defines a floor of the one or more cavities;
wherein the glass cladding layer defines sidewalls of the one or more cavities;
wherein the floor of the one or more cavities comprises a surface roughness of at most about 20 nm; and
wherein an angle formed between the sidewall and the floor of the one or more cavities is at most about 30°.

13. The structured glass article of claim 12 , wherein the glass cladding layer has a higher etch rate in an etchant than the glass core layer.

14. The structured glass article of claim 12 , wherein the photosensitivity of the glass cladding layer is greater than the photosensitivity of the glass base layer.

15. The structured glass article of claim 12 , wherein a difference between a first depth of one of the one or more cavities at a first position along the perimeter of the cavity and a second depth of the one of the one or more cavities at a second position along the perimeter of the cavity opposite the first position is at most about 5 μm.

16. The structured glass article of claim 12 , wherein the sidewalls of the one or more cavities are substantially straight.

17. The structured glass article of claim 12 , wherein a difference between a first width of one of the one or more cavities at a top of the cavity and a second width of the one of the one or more cavities at a bottom of the cavity is at most about 1 mm.

18. The structured glass article of claim 17 , wherein a depth of the one of the one or more cavities is at least about 50 μm.

19. A packaged integrated circuit, an optical device, or a microfluidic device comprising the structured glass article of claim 12 .

20. A method for making a reconstituted wafer- and/or panel-level package, the method comprising:
forming a plurality of cavities in a glass substrate comprising a glass cladding layer fused to a glass base layer; and
positioning an integrated circuit chip in each of the plurality of cavities in the glass substrate;
wherein a width of each of the cavities is no more than 20 μm larger than a width of the integrated circuit chip disposed therein; and
wherein a length of each of the cavities is no more than 20 μm larger than a length of the integrated circuit chip disposed therein.

Assignees

• Corning Inc

Inventors

• Boek Heather Debra
• Dohn Paul Bennett
• Kim Jin Su
• Li Aize
• Mcmahon Hugh Michael
• Yoon Jun Ro

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title