EOA circuit, display panel, and terminal

Patent metadata

Field	Value
Publication number	US-11367402-B2
Application number	US-202117338963-A
Country	US
Kind code	B2
Filing date	Jun 4, 2021
Priority date	Dec 6, 2018
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

The present disclosure relates to an EOA circuit, a display panel, and a terminal. The EOA circuit includes an output module and a control module; wherein the output module is configured to generate an output signal according to a first scanning signal and a clock signal, and the output module is further configured to reset the output signal from a high level to a low level within a period where the first scanning signal is an active level and a period where the clock signal is an inactive level; and the control module is configured to restore the output signal from the low level to the high level according to a second scanning signal within a period where the first scanning signal is at the inactive level.

First claim

What is claimed is:

1. An EOA circuit, comprising:
an output module, configured to generate an output signal according to a first scanning signal and a clock signal; wherein the output module is further configured to reset the output signal from a high level to a low level within a period where the first scanning signal is at an active level and a period where the clock signal is at an inactive level; and
a control module, configured to restore the output signal from the low level to the high level according to a second scanning signal within a period where the first scanning signal is at the inactive level.

2. The EOA circuit according to claim 1 , wherein the output module is constituted by an N-channel metal-oxide-semiconductor transistor.

3. The EOA circuit according to claim 2 , wherein the output module comprises:
an output terminal of the EOA circuit; and
a third transistor, a first electrode of the third transistor being connected to the clock signal, a second electrode of the third transistor being connected to the output terminal of the EOA circuit, and a third electrode of the third transistor is connected to the first scanning signal.

4. The EOA circuit according to claim 3 , wherein the control module comprises:
a first transistor, a first electrode of the first transistor being connected to a high level signal, a second electrode of the first transistor being connected to the second electrode of the third transistor, and a third electrode of the first transistor is connected to the second scanning signal.

5. The EOA circuit according to claim 4 , wherein the control module further comprises:
a second transistor, a first electrode of the second transistor being connected to the second electrode of the first transistor, a second electrode of the second transistor is connected to a low level signal, and a third electrode of the second transistor is shorted to the third electrode of the first transistor and connected to the second scanning signal.

6. The EOA circuit according to claim 5 , wherein the first transistor is a P-channel metal-oxide-semiconductor transistor, and the second transistor is an N-channel metal-oxide-semiconductor transistor.

7. The EOA circuit according to claim 5 , wherein the third transistor is turned on when the first scanning signal is at the high level.

8. The EOA circuit according to claim 5 , wherein the first transistor is turned off and the second transistor is turned on when the second scanning signal at the high level.

9. The EOA circuit according to claim 5 , wherein within a first time period, the first scanning signal is at the low level, and the second scanning signal is at the high level; the third transistor is turned off when the first scanning signal at the low level is applied to the third electrode of the third transistor, meanwhile the first transistor is turned off and the second transistor is turned on when the second scanning signal at the high level is applied to the third electrodes of the first transistor and the second transistor; and the low level signal pulls down the first electrode of the second transistor, meanwhile pulls down a voltage at the output terminal of the EOA circuit, such that the output terminal of the EOA circuit outputs the low level signal.

10. The EOA circuit according to claim 5 , wherein within a second time period, the third transistor is turned on when the first scanning signal at the high level is applied to the third electrode of the third transistor, meanwhile the first transistor is turned on and the second transistor is turned off when the second scanning signal at the low level is applied to the third electrodes of the first transistor and the second transistor; and
the clock signal at the high level is transmitted from the first electrode of the third transistor to the second electrode of the third transistor and transmitted to the output terminal of the EOA circuit, meanwhile the high level signal is transmitted from the first electrode of the first transistor to the second electrode of the first transistor and transmitted to the output terminal of the EOA circuit, such that the output terminal of the EOA circuit outputs the high level signal.

11. The EOA circuit according to claim 5 , wherein within a third time period, the first transistor is turned on and the second transistor is turned off when the second scanning signal at the low level is applied to the third electrodes of the first transistor and the second transistor, meanwhile the third transistor is turned on when the first scanning signal at the high level is applied to the third electrode of the third transistor; and
the high level signal is transmitted from the first electrode of the first transistor to the second electrode of the first transistor and transmitted to the output terminal of the EOA circuit, meanwhile the clock signal at the low level is transmitted from the first electrode of the third transistor to the second electrode of the third transistor and transmitted to the output terminal of the EOA circuit, such that the output terminal of the EOA circuit outputs the low level signal.

12. The EOA circuit according to claim 4 , wherein a size of the third transistor is greater than a size of the first transistor.

13. The EOA circuit according to claim 1 , wherein the control module is constituted by an N-channel metal-oxide-semiconductor transistor and a P-channel metal-oxide-semiconductor transistor.

14. The EOA circuit according to claim 1 , wherein the EOA circuit is a CMOS EOA circuit.

15. A display panel, comprising an EOA circuit disposed in a border region, wherein the EOA circuit comprises:
an output module, configured to generate an output signal according to a first scanning signal and a clock signal; wherein the output module is further configured to reset the output signal from a high level to a low level within a period where the first scanning signal is at an active level and a period where the clock signal is at an inactive level; and
a control module, configured to restore the output signal from the low level to the high level according to a second scanning signal within a period where the first scanning signal is at the inactive level.

16. The display panel according to claim 15 , wherein the display panel is a liquid crystal display panel.

17. The display panel according to claim 15 , wherein the display panel is an OLED display panel.

18. The display panel according to claim 15 , wherein the display panel is an AMOLED display panel.

19. A terminal, comprising a display panel with an EOA circuit disposed in a border region of the display panel; wherein the EOA circuit comprises: an output module, configured to generate an output signal according to a first scanning signal and a clock signal; wherein the output module is further configured to reset the output signal from a high level to a low level within a period where the first scanning signal is at an active level and a period where the clock signal is at an inactive level; and a control module, configured to restore the output signal from the low level to the high level according to a second scanning signal within a period where the first scanning signal is at the inactive level.

20. The terminal according to claim 19 , wherein the display panel is liquid crystal display panel, OLED display panel or AMOLED display panel.

Assignees

• Shenzhen Royole Technologies Co Ltd

Inventors

• Chen Dan
• Kim Jiha

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0232

  Special driving of display border areas · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title