Logic circuitry package

Patent metadata

Field	Value
Publication number	US-11364724-B2
Application number	US-201916768628-A
Country	US
Kind code	B2
Filing date	Oct 25, 2019
Priority date	Dec 3, 2018
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit including a memory storing a reference parameter. The at least one logic circuit is configured to receive, via the interface, a first request sent to a first address to read the reference parameter; and transmit, via the interface, the reference parameter in response to the first request. The at least one logic circuit is configured to receive, via the interface, a second request sent to a second address to implement a task; and implement the task to output a digital value via the interface in response to the second request. The reference parameter corresponds to the digital value.

First claim

The invention claimed is:

1. A logic circuitry package for a replaceable print apparatus component comprising an interface to communicate with a print apparatus logic circuit, and at least one logic circuit comprising:
a memory storing a reference parameter;
a controller; and
a machine readable storage medium storing instructions that when executed by the controller cause the at least one logic circuit to:
receive, via the interface, a first request sent to a first address to read the reference parameter;
transmit, via the interface, the reference parameter in response to the first request;
receive, via the interface, a second request sent to a second address to implement a task; and
implement the task to output a digital value via the interface in response to the second request,
wherein the reference parameter corresponds to the digital value, and
wherein the memory stores digitally signed data comprising the reference parameter.

2. The logic circuitry package of claim 1 , wherein the second address is one of a default second address and a reconfigured second address.

3. The logic circuitry package of claim 1 , wherein the reference parameter comprises one of a clock generator sample value, a calibration target value, a sensor target value, a sensor offset value, and a sensor slope value.

4. The logic circuitry package of claim 1 , wherein the memory stores a plurality of different reference parameters, and
wherein each reference parameter corresponds to a digital value output in response to implementing a corresponding task of the at least one logic circuit.

5. The logic circuitry package of claim 1 , wherein the memory stores a cryptographic key to cryptographically authenticate the reference parameter, and
wherein the machine readable storage medium stores instructions that when executed by the controller cause the at least one logic circuit to transmit the reference parameter cryptographically authenticated using the key in response to a cryptographically authenticated first request sent to the first address.

6. The logic circuitry package of claim 5 , wherein the machine readable storage medium stores instructions that when executed by the controller cause the at least one logic circuit to output the digital value corresponding to the reference parameter without cryptographically authenticating the digital value using the key.

7. The logic circuitry package of claim 1 , wherein the reference parameter corresponds to a predetermined temperature of the at least one logic circuit.

8. A replaceable print apparatus component comprising the logic circuitry package of claim 1 , further comprising:
a housing having a height, a width less than the height, and a length greater than the height, the height parallel to a vertical reference axis, and the width extending between two sides;
a print liquid reservoir within the housing; and
a print liquid output.

9. A logic circuitry package for a replaceable print apparatus component comprising an interface to communicate with a print apparatus logic circuit, and at least one logic circuit comprising:
a sensor;
a memory storing a reference parameter, the memory comprising at least one register;
a controller; and
a machine readable storage medium storing instructions that when executed by the controller cause the at least one logic circuit to:
receive, via the interface, a first request sent to a first address to read the reference parameter;
transmit, via the interface, the reference parameter in response to the first request;
receive, via the interface, a second request sent to a second address to implement a task; and
implement the task to output a digital value via the interface in response to the second request,
wherein the reference parameter corresponds to the digital value, and
wherein the task comprises one of a calibration function, a clock signal sample function, a sensor read function, and a register read function.

10. The logic circuitry package of claim 9 , wherein the second address is one of a default second address and a reconfigured second address.

11. The logic circuitry package of claim 9 , wherein the reference parameter comprises one of a clock generator sample value, a calibration target value, a sensor target value, a sensor offset value, and a sensor slope value.

12. The logic circuitry package of claim 9 , wherein the memory stores a plurality of different reference parameters, and
wherein each reference parameter corresponds to a digital value output in response to implementing a corresponding task of the at least one logic circuit.

13. The logic circuitry package of claim 9 , wherein the memory stores a cryptographic key to cryptographically authenticate the reference parameter, and
wherein the machine readable storage medium stores instructions that when executed by the controller cause the at least one logic circuit to transmit the reference parameter cryptographically authenticated using the key in response to a cryptographically authenticated first request sent to the first address.

14. The logic circuitry package of claim 13 , wherein the machine readable storage medium stores instructions that when executed by the controller cause the at least one logic circuit to output the digital value corresponding to the reference parameter without cryptographically authenticating the digital value using the key.

15. The logic circuitry package of claim 9 , wherein the reference parameter corresponds to a predetermined temperature of the at least one logic circuit.

16. A replaceable print apparatus component comprising the logic circuitry package of claim 9 , further comprising:
a housing having a height, a width less than the height, and a length greater than the height, the height parallel to a vertical reference axis, and the width extending between two sides;
a print liquid reservoir within the housing; and
a print liquid output.

17. A logic circuitry package for a replaceable print apparatus component, the logic circuitry package comprising:
an interface;
a first logic circuit configured to respond to communications via the interface, the first logic circuit comprising a memory storing at least one reference parameter, and the first logic circuit configured to:
receive, via the interface, a request to read the at least one reference parameter; and
transmit, via the interface, the at least one reference parameter in response to the request;

a second logic circuit configured to respond to communications via the interface, the second logic circuit configured to:
receive, via the interface, a request to implement a task; and
implement the task to output a digital value via the interface;

wherein the at least one reference parameter corresponds to the digital value.

18. The logic circuitry package of claim 17 , wherein the memory stores digitally signed data comprising the at least one reference parameter.

19. The logic circuitry package of claim 17 , wherein the first logic circuit is configured to respond to communications sent to a first address, and
wherein the second logic circuit is configured to respond to communications sent to a second address.

20. The logic circuitry package of claim 19 , wherein the memory stores a cryptographic key to cryptographically authenticate the at least one reference parameter, and
wherein the first logic circuit is configured to transmit the at least one reference parameter cryptographically authenticated using the key in response to a cryptographically authe

Assignees

• Hewlett Packard Development Co

Inventors

• Gardner James Michael
• Novak David B

Classifications

• G06F13/4291

  using a clocked protocol · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• B41J2002/17586

  using ink bag deformation for ink level indication · CPC title

• B33Y30/00

  Apparatus for additive manufacturing; Details thereof or accessories therefor · CPC title

• G01F23/247

  for discrete levels · CPC title