Selectors for memory elements

Patent metadata

Field	Value
Publication number	US-11364717-B2
Application number	US-202117454069-A
Country	US
Kind code	B2
Filing date	Nov 9, 2021
Priority date	Jul 6, 2017
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

First claim

What is claimed is:

1. A circuit for a print cartridge, comprising:
a first memory element;
a decoder to receive an address and to enable the first memory element for access in response to the address;
a data line;
an input line; and
a selector responsive to the data line to select the first memory element, wherein the selector is to select the first memory element responsive to the data line having a first value, wherein the data line is to communicate data of a second memory element in response to the second memory element being enabled for access,
the input line to communicate data of the first memory element in response to the first memory element being selected by the selector.

2. The circuit of claim 1 , further comprising:
a second decoder to receive a further address and to enable the second memory element for access in response to the further address.

3. The circuit of claim 1 , wherein the decoder comprises a shift register decoder including multiple shift registers to receive address data bits and a select input to receive a select signal.

4. The circuit of claim 1 , wherein the selector comprises:
a first switch connected to the first memory element, the first switch to activate when the data line has the first value.

5. The circuit of claim 4 , wherein the first switch comprises a first transistor connected in series with the first memory element, and
wherein a gate of the first transistor is connected to the data line.

6. The circuit of claim 1 , wherein the selector comprises:
a first switch to connect an output of the decoder to a first transistor in series with the first memory element in response to the data line having the first value.

7. The circuit of claim 6 , wherein the first switch is to activate in response to the data line having the first value, and a node of the first switch is connected to a gate of the first transistor.

8. The circuit of claim 1 , wherein the first memory element and/or the second memory element are provided on one or more dies separate from a fluid ejection die including a nozzle.

9. An apparatus comprising:
one or more dies that comprise:
a first memory element;
a second memory element different from the first memory element;
an input line coupled to the first memory element;
a data line to communicate data of the second memory element; and
a selector responsive to the data line to select the first memory element, wherein the selector is to select the first memory element responsive to the data line having a first value,
the input line to communicate data of the first memory element in response to the first memory element being selected by the selector.

10. The apparatus of claim 9 , wherein the one or more dies are separate from a fluid ejection die that comprises a nozzle.

11. The apparatus of claim 10 , further comprising the fluid ejection die, wherein the input line is to control activation of the nozzle by carrying a fire signal to the nozzle.

12. The apparatus of claim 9 , wherein:
the first memory element is part of a first memory storing data related to a nozzle array; and
the second memory element is part of an ID memory storing identification data.

13. The apparatus of claim 12 , wherein the ID memory and the first memory are implemented with different types of memories to form a hybrid memory arrangement.

14. The apparatus of claim 12 , wherein the first memory is implemented with a fuse memory, where the fuse memory includes an array of fuses that can be selectively blown or not blown to program data into the first memory.

15. The apparatus of claim 12 , wherein the selector comprises a transistor connected in series with the first memory element, and a gate of the transistor is controlled by the data line.

16. The apparatus of claim 12 , wherein the first memory comprises:
the first memory element;
first transistors, wherein the first memory element is connected in series with the first transistors between the input line and a reference voltage;
second transistors of a decoder, wherein:
a gate of one of the first transistors is connected to the data line and the one of the first transistors is part of the selector, and
a gate of a further one of the first transistors is connected to the decoder to control the further one of the first transistors based on an address input to the decoder.

17. The apparatus of claim 12 , wherein the ID memory comprises:
the second memory element;
first transistors connected in series between the data line and a reference voltage;
wherein:
when the first transistors are turned on, the second memory element is addressed such that data of the second memory element are communicated over the data line, and
gates of the first transistors are connected to outputs of a shift register decoder that receives address data bits.

18. A print cartridge comprising:
a circuit comprising:
a first memory element;
a decoder to receive an address and to enable the first memory element for access in response to the address;
a data line, wherein the data line is different from an address line to carry the address;
an input line; and
a selector responsive to the data line to select the first memory element, wherein the selector is to select the first memory element responsive to the data line having a first value, wherein the data line is to communicate data of a second memory element in response to the second memory element being enabled for access,
the input line to communicate data of the first memory element in response to the first memory element being selected by the selector.

19. The print cartridge of claim 18 , wherein the circuit further comprises:
a second decoder to receive a further address and to enable the second memory element for access in response to the further address.

20. The print cartridge of claim 18 , wherein the selector comprises:
a first switch connected to the first memory element, the first switch to activate when the data line has the first value.

Assignees

• Hewlett Packard Development Co

Inventors

• Ng Boon Bing
• Pan Rui
• Sudhakar Mohan Kumar
• Hall Brendan

Classifications

• B41J2/04541 Primary

  Specific driving circuit · CPC title

• B41J2202/17

  Readable information on the head · CPC title

• B41J2/0458

  controlling heads based on heating elements forming bubbles · CPC title

• B41J2/0455 Primary

  Details of switching sections of circuit, e.g. transistors · CPC title

• B41J2/0452 Primary

  reducing demand in current or voltage · CPC title