Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11361995-B2
Application number	US-202117146597-A
Country	US
Kind code	B2
Filing date	Jan 12, 2021
Priority date	Aug 20, 2018
Publication date	Jun 14, 2022
Grant date	Jun 14, 2022

Abstract

A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a pixel isolation pattern and a through via extending through a substrate in a pixel region, the substrate including the pixel region and an input/output region, and the through via being spaced apart from the pixel isolation pattern,
wherein the pixel isolation pattern has a lattice shape in which some portions are cut in a plan view, the through via is formed at a cutting portion of the pixel isolation pattern having the lattice shape, the cutting portion is an area cut from the pixel isolation pattern, and the pixel isolation pattern and the through via define a unit pixel region;
forming a via on an inner wall of a first trench on the substrate in the input/output region, wherein the via comprises a first conductive material;
forming a first insulating interlayer on the substrate, wherein the first insulating interlayer covers the via and partially fills the first trench, and the first insulating interlayer has a non-flat upper surface;
forming a polishing stop layer on the first insulating interlayer;
forming a second insulating interlayer on the polishing stop layer, wherein the second insulating interlayer fills a remaining portion of the first trench;
planarizing the second insulating interlayer until the polishing stop layer is exposed; and
etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the first trench are removed.

2. The method of claim 1 , wherein the dry etching process is performed using an etching gas of which an etching selectivity between the polishing stop layer and the first and second insulating interlayers is about 0.5:1.5 to about 1.5:0.5.

3. The method of claim 2 , wherein the etching gas comprises at least one of fluorocarbon (CH 4 ), fluoroform (CHF 3 ) or oxygen (O 2 ).

4. The method of claim 1 , wherein planarizing the second insulating interlayer is performed using a chemical mechanical polishing (CMP) process.

5. The method of claim 4 , wherein the CMP process is performed using a slurry of which a polishing selectivity between the second insulating interlayer and the polishing stop layer is about equal to or greater than about 10:1.

6. The method of claim 1 , wherein the polishing stop layer comprises a nitride or a carbide.

7. The method of claim 6 , wherein the polishing stop layer comprises at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), or silicon oxycarbide (SiOC).

8. The method of claim 1 , further comprising:
forming a pad on the substrate in a pad region, the pad region being disposed between the pixel region and the input/output region, wherein the pad comprises a second conductive material; and
forming an interference prevention pattern on the substrate in the pixel region, wherein the interference prevention pattern comprises a third conductive material,
wherein the first insulating interlayer covers the pad and the interference prevention pattern.

9. The method of claim 8 , wherein the pad fills a second trench on the substrate in the pad region and is formed on an upper surface of the substrate adjacent to the second trench.

10. The method of claim 8 , wherein the pad is formed in a second trench on the substrate.

11. The method of claim 8 , wherein the interference prevention pattern overlaps the pixel isolation pattern in a direction substantially vertical to an upper surface of the substrate, and the interference prevention pattern does not overlap the substrate in the direction.

12. A method of manufacturing a semiconductor device, comprising:
forming a pixel isolation pattern and a through via extending through a substrate in a pixel region, the substrate including the pixel region and an input/output region, and the through via being spaced apart from the pixel isolation pattern,
wherein the pixel isolation pattern has a lattice shape in which some portions are cut in a plan view, the through via is formed at a cutting portion of the pixel isolation pattern having the lattice shape, the cutting portion is an area cut from the pixel isolation pattern, and the pixel isolation pattern and the through via define a unit pixel region;
forming an opening through the substrate in the input/output region;
forming a via on an inner wall of the opening;
forming an interference prevention pattern on an upper surface of the pixel isolation pattern;
forming a first insulating interlayer on the substrate, wherein the first insulating interlayer covers the via and the interference prevention pattern;
forming a polishing stop layer on the first insulating interlayer;
forming a second insulating interlayer on the polishing stop layer, wherein the second insulating interlayer fills a remaining portion of the opening;
planarizing the second insulating interlayer until the polishing stop layer is exposed; and
etching the polishing stop layer and the first and second insulating interlayers using a dry etching process.

13. The method of claim 12 , wherein the first insulating interlayer covering the via and the interference prevention pattern has a non-flat upper surface before the dry etching process is performed, and the first insulating interlayer covering the via and the interference prevention pattern has a substantially flat upper surface after the dry etching process has been performed.

14. The method of claim 12 , wherein the dry etching process is performed until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the opening are entirely removed.

15. The method of claim 12 , wherein the substrate further comprises a pad region disposed between the pixel region and the input/output region,
wherein forming the via and the interference prevention pattern comprises forming a pad on the substrate in the pad region, and the first insulating interlayer covers the pad.

16. The method of claim 15 , wherein forming the pad comprises forming a contact plug,
wherein the contact plug extends through the substrate and is connected to the pad.

17. The method of claim 12 , wherein the interference prevention pattern does not overlap the substrate in a direction substantially vertical to an upper surface of the substrate.

18. A method of manufacturing a semiconductor device, comprising:
forming a pixel isolation pattern and a through via extending through a substrate in a pixel region, the substrate including the pixel region and an input/output region and a first surface and a second surface disposed opposite to the first surface, and the through via being spaced apart from the pixel isolation pattern,
wherein the pixel isolation pattern has a lattice shape in which some portions are cut in a plan view, the through via is formed at a cutting portion of the pixel isolation pattern having the lattice shape, the cutting portion is an area cut from the pixel isolation pattern, and the pixel isolation pattern and the through via define a unit pixel region;
forming a first insulating interlayer on the first surface of the substrate, wherein the first insulating interlayer comprises a plurality of wiring structures;
forming an opening through the substrate in the input/output region, wherein the opening exposes at least one of the wiring structures;
forming a via on the exposed at least one of the wiring structur

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Seung-Hoon
• Koo Ja-Eung
• Kim Kwan-Sik
• Kim Dong-Chan
• Yoon Il-Young
• Cho Man-Geun

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title