Apparatus and method for pausing processor trace for efficient analysis

Patent metadata

Field	Value
Publication number	US-11360876-B2
Application number	US-202016845512-A
Country	US
Kind code	B2
Filing date	Apr 10, 2020
Priority date	Dec 29, 2017
Publication date	Jun 14, 2022
Grant date	Jun 14, 2022

Abstract

Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

First claim

What is claimed is:

1. A processing apparatus comprising:
at least one processor; and
a compiler to:
insert a resume tracing instruction into instrumented code prior to at least one call to un-instrumented code, wherein the at least one call to the un-instrumented code is identified in a trace policy;
execute the resume tracing instruction, when enabled by a trace register, to selectively add processor tracing to the at least one call to the un-instrumented code; and
execute the at least one call to the un-instrumented code.

2. The processing apparatus of claim 1 , wherein the compiler is further to:
determine that a return call from the un-instrumented code has been executed; and
insert a pause tracing instruction into the instrumented code after the return call, wherein the trace policy further identifies the return call.

3. The processing apparatus of claim 1 , wherein the resume tracing instruction toggles a bit in the trace register.

4. The processing apparatus of claim 3 , wherein a control packet is updated in trace data when the resume tracing instruction is executed, the control packet indicating a value of the bit in the trace register.

5. The processing apparatus of claim 1 , wherein to insert the resume tracing instruction into the instrumented code prior to the at least one call to the un-instrumented code, the compiler is further to:
add an instruction prefix for the resume tracing instruction to the instrumented code.

6. The processing apparatus of claim 1 , wherein the resume tracing instruction is enabled for the instrumented code based on a value of at least one first field of a model specific register, and wherein the resume tracing instruction modifies a value of at least one second field of the model specific register, the at least one second field exposed by a security mask.

7. A method comprising:
inserting a resume tracing instruction into instrumented code prior to at least one call to un-instrumented code;
executing the resume tracing instruction, when enabled by a trace register, to selectively add processor tracing to the at least one call to the un-instrumented code, wherein the resume tracing instruction is to toggle a bit in the trace register; and
executing the at least one call to the un-instrumented code.

8. The method of claim 7 , wherein the at least one call to the un-instrumented code is identified in a trace policy.

9. The method of claim 8 , further comprising:
determining, by a compiler, that a return call from the un-instrumented code has been executed; and
inserting a pause tracing instruction into the instrumented code after the return call, wherein the trace policy further identifies the return call.

10. The method of claim 7 , wherein a control packet is updated in trace data when the resume tracing instruction is executed, the control packet indicating a value of the bit in the trace register.

11. The method of claim 7 , wherein inserting the resume tracing instruction into the instrumented code prior to the at least one call to the un-instrumented code further comprises:
adding an instruction prefix for the resume tracing instruction to the instrumented code.

12. The method of claim 7 , wherein the resume tracing instruction is enabled for the instrumented code based on a value of at least one first field of a model specific register, and wherein the resume tracing instruction modifies a value of at least one second field of the model specific register, the at least one second field exposed by a security mask.

13. A non-transitory computer readable storage medium including instructions stored thereon which, when executed by a processor, cause the processor to:
insert a resume tracing instruction into instrumented code prior to at least one call to un-instrumented code, wherein the resume tracing instruction is enabled for the instrumented code based on a value of at least one first field of a model specific register, and wherein the resume tracing instruction modifies a value of at least one second field of the model specific register, the at least one second field exposed by a security mask;
execute the resume tracing instruction, when enabled by a trace register, to selectively add processor tracing to the at least one call to the un-instrumented code; and
execute the at least one call to the un-instrumented code.

14. The non-transitory computer readable storage medium of claim 13 , wherein the at least one call to the un-instrumented code is identified in a trace policy.

15. The non-transitory computer readable storage medium of claim 14 , wherein the instructions, when executed, further cause the processor to:
determine, by a compiler, that a return call from the un-instrumented code has been executed; and
insert a pause tracing instruction into the instrumented code after the return call, wherein the trace policy further identifies the return call.

16. The non-transitory computer readable storage medium of claim 13 , wherein the resume tracing instruction toggles a bit in the trace register.

17. The non-transitory computer readable storage medium of claim 16 , wherein a control packet is updated in trace data when the resume tracing instruction is executed, the control packet indicating a value of the bit in the trace register.

18. The non-transitory computer readable storage medium of claim 13 , wherein to insert the resume tracing instruction into the instrumented code prior to the at least one call to the un-instrumented code further causes the processor to:
add an instruction prefix for the resume tracing instruction to the instrumented code.

Assignees

• Intel Corp

Inventors

• Lemay Michael
• Strong Beeman

Classifications

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F21/56 Primary

  Computer malware detection or handling, e.g. anti-virus arrangements · CPC title

• G06F2221/033

  Test or assess software · CPC title

• G06F11/2247

  Verification or detection of system hardware configuration · CPC title