Process flow for hybrid TFT-based micro display projector

Patent metadata

Field	Value
Publication number	US-11355665-B2
Application number	US-202016780486-A
Country	US
Kind code	B2
Filing date	Feb 3, 2020
Priority date	Jun 19, 2019
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

Disclosed herein are techniques for forming a thin-film circuit layer on an array of light-emitting diodes (LEDs). LEDs in the array of LEDs can be singulated by various processes, such as etching and ion implantation. Singulating LEDs can be performed before or after forming the thin-film circuit layer on the array of LEDs. The array of LEDs can be bonded to a transparent or non-transparent substrate.

First claim

What is claimed is:

1. A method comprising:
obtaining an epitaxial structure, wherein the epitaxial structure is a layered structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light-emitting layer between the first doped semiconductor layer and the second doped semiconductor layer;
isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer for forming a plurality of light emitting diodes (LEDs);
depositing a thin-film circuit layer without a substrate onto the epitaxial structure, wherein depositing the thin-film circuit layer comprises:
depositing a first thin-film layer on the epitaxial structure;
forming, in the first thin-film layer, a plurality of transistors;
depositing a second thin-film layer on the first thin-film layer; and
forming, in the second thin-film layer, interconnects for the plurality of transistors; and

bonding the thin-film circuit layer to a backplane.

2. The method of claim 1 , further comprising forming light extraction elements to the epitaxial structure to couple light out of the light-emitting layer.

3. The method of claim 1 , wherein the first doped semiconductor layer is an n-doped layer, and the second doped semiconductor layer is a p-doped layer.

4. The method of claim 1 , further comprising:
bonding a temporary carrier to the epitaxial structure before depositing the thin-film circuit layer to the epitaxial structure; and
removing the temporary carrier after bonding the second thin-film layer of the thin-film circuit layer to the backplane.

5. The method of claim 1 , wherein isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer comprises etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer.

6. The method of claim 5 , wherein the second doped semiconductor layer is p-doped, and the method further comprises bonding a temporary carrier to the second doped semiconductor layer and removing a first substrate from the epitaxial structure, wherein the first substrate was closer to the first doped semiconductor layer than the second doped semiconductor layer before removal of the first substrate.

7. The method of claim 5 , wherein etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer occurs before depositing the thin-film circuit layer to the epitaxial structure.

8. The method of claim 5 , wherein etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer occurs after bonding the thin-film circuit layer to the backplane.

9. The method of claim 5 , wherein etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer occurs after depositing the first thin-film layer and before depositing the second thin-film layer.

10. The method of claim 9 , wherein etching the first doped semiconductor layer, the second doped semiconductor layer, or both the first doped semiconductor layer and the second doped semiconductor layer comprises etching both the first doped semiconductor layer and the second doped semiconductor layer, and further includes etching the first thin-film layer.

11. The method of claim 1 , further comprising:
bonding a temporary carrier to the epitaxial structure, wherein:
the second doped semiconductor layer is between the first doped semiconductor layer and the temporary carrier; and
the first doped semiconductor layer is between the second doped semiconductor layer and a first substrate of the epitaxial structure;

removing the first substrate from the epitaxial structure; and
wherein isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer comprises implanting ions in selected regions of the first doped semiconductor layer to isolate portions of the first doped semiconductor layer, before depositing the thin-film circuit layer on the epitaxial structure.

12. The method of claim 11 , further comprising implanting ions in the second doped semiconductor layer before bonding the temporary carrier to the epitaxial structure.

13. The method of claim 1 , further comprising:
bonding a temporary carrier to the epitaxial structure before removing a first substrate from the epitaxial structure; and
wherein isolating portions of the first doped semiconductor layer, isolating portions of the second doped semiconductor layer, or isolating portions of both the first doped semiconductor layer and the second doped semiconductor layer comprises implanting ions in the second doped semiconductor layer before bonding the temporary carrier to the epitaxial structure.

14. The method of claim 1 , further comprising performing backside processing on the epitaxial structure to form a mesa shape.

15. The method of claim 1 , further comprising performing front-side processing on the epitaxial structure to create light-extraction features.

16. The method of claim 1 , wherein the backplane comprises memory circuits and modulation circuits, and the plurality of transistors in the thin-film circuit layer form a multiplexor.

17. The method of claim 1 , wherein the backplane comprises modulation circuits, and the plurality of transistors in the thin-film circuit layer form a multiplexor and memory circuits.

18. The method of claim 1 , wherein the plurality of transistors in the thin-film circuit layer form a multiplexor, memory circuits, and modulation circuits.

Assignees

• Facebook Tech Llc

Inventors

• Fabien Chloe Astrid Marie
• Grundmann Michael

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10H20/036

  of packages · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/01 Primary

  Manufacture or treatment · CPC title