Tiled light emitting diode display panel having different resistance per unit length signal lines

US11355473B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11355473-B2
Application numberUS-202016902639-A
CountryUS
Kind codeB2
Filing dateJun 16, 2020
Priority dateJun 16, 2020
Publication dateJun 7, 2022
Grant dateJun 7, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A tiled light emitting diode (LED) display panel includes multiple flexible back plates arranged in tiles. Each flexible back plate has multiple through holes formed thereon. A pixel array is formed by multiple LEDs on the flexible back plates and collectively defines multiple pixels. Each pixel includes one LED and thin-film transistor (TFT) circuits disposed on a first side of a corresponding flexible back plate. A printed circuit board (PCB) is disposed at a second side of the flexible back plates. A third side of the PCB faces the second side of the flexible back plates and has multiple signal lines formed thereon. The LEDs and the TFT circuits of the pixels are electrically connected to the corresponding signal lines via multiple conductive structures formed in the through holes. A resistance per unit length of each flexible back plates is greater than a resistance per unit length of the PCB.

First claim

Opening claim text (preview).

What is claimed is: 1. A tiled light emitting diode (LED) display panel, comprising: a plurality of flexible back plates arranged in tiles, wherein each of the flexible back plates has a first side and a second side opposite to each other, and has a plurality of through holes formed thereon; a pixel array formed by a plurality of LEDs on the flexible back plates, collectively defining a plurality of pixels, wherein each of the pixels comprises one of the LEDs and thin-film transistor (TFT) circuits disposed on the first side of a corresponding one of the flexible back plates; a printed circuit board (PCB) disposed at the second side of the flexible back plates, wherein the PCB has a third side and a fourth side opposite to each other, and the third side of the PCB faces the second side of the flexible back plates; a plurality of signal lines formed on the third side of the PCB; a plurality of sub signal lines formed on the flexible back plates, correspondingly electrically connected to the LEDs and the TFT circuits of the pixels; and a plurality of conductive structures formed in the through holes, wherein the sub signal lines are electrically connected to the corresponding signal lines via the conductive structures, wherein a resistance per unit length of each of the sub signal lines formed on each of the flexible back plates is greater than a resistance per unit length of the PCB and the signal lines formed thereon. 2. The tiled LED display panel of claim 1 , wherein a thickness and a width of each of the signal lines are greater than a thickness and a width of each of the sub signal lines. 3. The tiled LED display panel of claim 1 , wherein: the signal lines comprise a plurality of data lines extending along a first direction, a plurality of scan lines extending along a second direction, and a plurality of power lines; and the sub signal lines comprise a plurality of sub data lines extending along the first direction, a plurality of sub scan lines extending along the second direction, and a plurality of sub power lines, each of the sub data lines is electrically connected to a corresponding one of the data lines, each of the sub scan lines is electrically connected to a corresponding one of the scan lines, and each of the sub power lines is electrically connected to a corresponding one of the power lines. 4. The tiled LED display panel of claim 3 , wherein the through holes are aligned in a direction different from the first direction and the second direction. 5. The tiled LED display panel of claim 1 , wherein each of the through holes has a diameter greater than 10 um. 6. The tiled LED display panel of claim 1 , wherein the conductive structures are electrically connected to the corresponding signal lines through soldering or by anisotropic conductive films (ACFs). 7. The tiled LED display panel of claim 1 , wherein the through holes are formed at a border area of the flexible back plates. 8. The tiled LED display panel of claim 1 , wherein the through holes are formed in an active area of the flexible back plates. 9. The tiled LED display panel of claim 1 , wherein the LEDs are organic LEDs (OLEDs), and each of the flexible back plates is further provided with a thin-film encapsulation (TFE) layer divided in at least two regions to cover the OLEDs, and the TFE layer in each of the at least two regions covers at least one of the OLEDs on each of the flexible back plates. 10. The tiled LED display panel of claim 1 , further comprising at least one signal integrated circuit (IC) disposed on the PCB, configured to provide signals to the signal lines correspondingly. 11. The tiled LED display panel of claim 10 , wherein the at least one signal IC are disposed at a border area on the third side of the PCB. 12. The tiled LED display panel of claim 10 , wherein the at least one signal IC are disposed on the fourth side of the PCB. 13. The tiled LED display panel of claim 1 , wherein for a respective through hole of the through holes, one of the TFT circuits corresponding to the respective through hole and a respective conductive structure of the conductive structures corresponding to the respective through hole is formed with a hole corresponding to the respective through hole. 14. The tiled LED display panel of claim 13 , wherein for the respective through hole of the through holes, the TFT circuits corresponding to the respective through hole has a surrounding portion surrounding the hole and the respective through hole, and the respective conductive structure is formed by a solder material attached to a side wall of the through hole and connected to the surrounding portion. 15. The tiled LED display panel of claim 13 , wherein for the respective through hole of the through holes, the TFT circuits corresponding to the respective through hole has a surrounding portion surrounding the hole and the respective through hole and attached to a side wall of the through hole, and the respective conductive structure is formed by a solder material attached to the side wall of the through hole and connected to the surrounding portion. 16. The tiled LED display panel of claim 13 , wherein for the respective through hole of the through holes, the TFT circuits corresponding to the respective through hole has a filler portion filled in a part of the respective through hole, and the respective conductive structure is formed by a solder material having the hole and connected to the filler portion. 17. A light emitting diode (LED) display panel, comprising: a flexible back plate having a first side and a second side opposite to each other, and a plurality of through holes formed thereon; a pixel array formed by a plurality of LEDs on the flexible back plate, collectively defining a plurality of pixels, wherein each of the pixels comprises one of the LEDs and thin-film transistor (TFT) circuits disposed on the first side of the flexible back plate; a printed circuit board (PCB) disposed at the second side of the flexible back plate, wherein the PCB has a third side and a fourth side opposite to each other, and the third side of the PCB faces the second side of the flexible back plate; a plurality of signal lines formed on the third side of the PCB; a plurality of sub signal lines formed on the flexible back plates, correspondingly electrically connected to the LEDs and the TFT circuits of the pixels; and a plurality of conductive structures formed in the through holes, wherein the sub signal lines are electrically connected to the corresponding signal lines via the conductive structures, wherein for a respective through hole of the through holes, one of the TFT circuits corresponding to the respective through hole and a respective conductive structure of the conductive structures corresponding to the respective through hole is formed with a hole corresponding to the respective through hole. 18. The LED display panel of claim 17 , wherein a resistance per unit length of the sub signal lines formed on the flexible back plate is greater than a resistance per unit length of the PCB and the signal lines formed thereon. 19. The LED display panel of claim 17 , wherein: the signal lines comprise a plurality of data lines extending along a first direction, a plurality of scan lines extending along a second direction, and a plurality of power lines; and the sub signal lines comprise a plurality of sub data lines extending along the first direction, a plurality of sub scan lines extending along the second direction, and a plurality of sub power lines, each of

Assignees

Inventors

Classifications

  • H10W90/00Primary

    Package configurations · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • characterised by changes in properties of the die-attach connectors during connecting · CPC title

  • Soldering or alloying · CPC title

  • Active alignment, e.g. using optical alignment using marks or sensors · CPC title

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What does patent US11355473B2 cover?
A tiled light emitting diode (LED) display panel includes multiple flexible back plates arranged in tiles. Each flexible back plate has multiple through holes formed thereon. A pixel array is formed by multiple LEDs on the flexible back plates and collectively defines multiple pixels. Each pixel includes one LED and thin-film transistor (TFT) circuits disposed on a first side of a corresponding…
Who is the assignee on this patent?
A U Vista Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 07 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).