Driving passive light emitting diode array having a driver for outputting switching output signals

Patent metadata

Field	Value
Publication number	US-11355058-B2
Application number	US-202117301045-A
Country	US
Kind code	B2
Filing date	Mar 23, 2021
Priority date	Mar 26, 2020
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A driving device includes a control unit, a switch unit and a driver unit. The control unit is configured to generate a gray scale output and a synchronization signal. The switch unit is coupled to an LED array, and switches among different conduction states based on a switching output. The driver unit is coupled to the control unit, the switch unit and the LED array. The driver unit generates the switching output based on a clock signal and the synchronization signal, and generates drive outputs for receipt by the LED array based on the clock signal, the gray scale output and the synchronization signal, so as to drive the LED array to emit light.

First claim

What is claimed is:

1. A driving device operatively associated with a first light emitting diode (LED) array, and comprising:
a controller configured to generate a gray scale output and a synchronization signal;
a first switch adapted to be coupled to the first LED array, to receive a first switching output, and to switch among different conduction states based on the first switching output; and
a first driver coupled to said controller and said first switch, adapted to be further coupled to the first LED array, and to receive the gray scale output and the synchronization signal from said controller,
wherein said first driver generates the first switching output for receipt by said first switch based on a first clock signal and the synchronization signal, and generates a plurality of first drive outputs for receipt by the first LED array based on the first clock signal, the gray scale output and the synchronization signal; and
wherein the first LED array is driven to emit light by said first switch based on the first switching output and by said first driver through the first drive outputs.

2. The driving device of claim 1 , wherein:
the first switching output includes a plurality of switching signals;
said first switch includes a plurality of switches; and
each of said switches has a first terminal that is to receive an input voltage, a second terminal that is adapted to be coupled to the first LED array, and a control terminal that is coupled to said first driver to receive a respective one of the switching signals therefrom.

3. The driving device of claim 2 , the first LED array including a plurality of LEDs, each of the LEDs having an anode and a cathode, wherein:
said first driver is adapted to be coupled to the cathodes of the LEDs; and
said second terminal of each of said switches is adapted to be coupled to the anodes of corresponding ones of the LEDs.

4. The driving device of claim 1 , wherein:
the first switching output includes a plurality of switching signals;
said first driver is to further receive an input voltage, and to acquire the first drive outputs from the input voltage;
said first switch includes a plurality of switches; and
each of said switches has a first terminal that is to receive a ground voltage, a second terminal that is adapted to be coupled to the first LED array, and a control terminal that is coupled to said first driver to receive a respective one of the switching signals therefrom.

5. The driving device of claim 4 , the first LED array including a plurality of LEDs, each of the LEDs having an anode and a cathode, wherein:
said first driver is adapted to be coupled to the anodes of the LEDs; and
said second terminal of each of said switches is adapted to be coupled to the cathodes of corresponding ones of the LEDs.

6. The driving device of claim 1 , wherein:
said first driver generates a number (M) of the first clock signals;
said first driver includes a number (M) of first driver chips, where M≥2; and
each of said first driver chips generates a respective one of the first clock signals.

7. The driving device of claim 6 , wherein:
the gray scale output includes a second clock signal and a serial input signal;
each of said first driver chips has a drive output pin set that provides a respective one of the first drive outputs, a switching output pin set, a control input pin, a control output pin, a gray scale input pin, a gray scale output pin, a synchronization pin, and a clock pin that is coupled to said controller to receive the second clock signal;
for a first one of said first driver chips, said drive output pin set thereof is adapted to be coupled to the first LED array, said switching output pin set thereof is coupled to said first switch, said control input pin thereof is to receive a predetermined bias voltage, and said gray scale input pin thereof and said synchronization pin thereof are coupled to said controller to respectively receive the serial input signal and the synchronization signal;
said first one of said first driver chips generates the first switching output based on the first clock signal generated thereby and the synchronization signal, generates the respective one of the first drive outputs based on the first clock signal generated thereby, the second clock signal, the serial input signal and the synchronization signal, and generates a control signal that contains synchronization pulses of the synchronization signal and a line scan command which indicates when the respective one of the first drive outputs changes;
said first one of said first driver chips outputs the first switching output at said switching output pin set thereof, outputs the respective one of the first drive outputs at said drive output pin set thereof, outputs the control signal at the control output pin thereof, and outputs the serial input signal at the gray scale output pin thereof;
for an m th one of said first driver chips, said drive output pin set thereof is adapted to be coupled to the first LED array, said control input pin thereof is coupled to said control output pin of said first one of said first driver chips to receive the control signal, said gray scale input pin thereof is coupled to said gray scale output pin of an (m-1) th one of said first driver chips to receive the serial input signal, and said synchronization pin is coupled to ground, where 2≤m≤M; and
said m th one of said first driver chips generates the respective one of the first drive outputs based on the first clock signal generated thereby, the second clock signal, the serial input signal and the control signal, outputs the respective one of the first drive outputs at said drive output pin set thereof, and outputs the serial input signal at the gray scale output pin thereof.

8. The driving device of claim 7 , further operatively associated with a second LED array, and further comprising:
a second switch adapted to be coupled to the second LED array, to receive a second switching output, and to switch among different conduction states based on the second switching output; and
a second driver chip coupled to said controller, said first driver and said second switch, adapted to be further coupled to the second LED array, to receive the second clock signal from said controller, and to further receive the serial input signal and the control signal from said first driver,
wherein said second driver chip generates the second switching output for receipt by said second switch based on a respective first clock signal and the control signal, and generates a second drive output for receipt by the second LED array based on the respective first clock signal, the second clock signal, the serial input signal and the control signal; and
wherein the second LED array is driven to emit light by said second switch based on the second switching output and by said second driver chip through the second drive output.

9. The driving device of claim 6 , wherein:
the gray scale output includes a second clock signal and a serial input signal;
each of said first driver chips has a drive output pin set that provides a respective one of the first drive outputs, a switching output pin set, a control input pin, a control output pin, a gray scale input pin, a gray scale output pin, a synchronization pin, and a clock pin that is coupled to said controller to receive the second clock signal;
for a first one of said first driver chips, said drive output pin set thereof is adapted to be coupled to the first LED array, said switching output pin set thereof is coupled to said first switch, said control input pin thereof is to receive a predetermined bias voltage, and said gray scale input pin thereof and said synchronization pin the

Assignees

• Macroblock Inc

Inventors

• Huang Ping-Kai
• Li Chun-Yi

Classifications

• G09G3/2007

  Display of intermediate tones · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title

• G09G3/2096

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title