Integrated circuit for nonlinear data encoding

Patent metadata

Field	Value
Publication number	US-11355050-B2
Application number	US-202017129668-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Oct 7, 2015
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A method of image processing, the method including performing linear processing of an input data signal encoded with a nonlinear function to generate a linear representation of the input data signal including linearized image data, and using an integrated circuit to generate a processed linear image by nonlinearly quantizing the linearized image data to generate nonlinear quantized data, generating a memory address based on the nonlinear quantized data, and accessing a lookup table based on the generated memory address.

First claim

What is claimed is:

1. A method of nonlinear encoding, the method comprising:
receiving a linearized data;
identifying a data block that contains the linearized data, wherein the data block corresponds to a boundary slice, an offset, and a shift parameter;
generating most significant bits of the linearized data according to the shift parameter;
generating most significant bits of the boundary slice of a previous data block according to the shift parameter; and
generating a nonlinear quantized data according to the most significant bits of the linearized data, the offset, and the most significant bits of the boundary slice.

2. The method of claim 1 , further comprising:
receiving an image data encoded with a nonlinear function; and
performing linear processing on the image data to generate the linearized data.

3. The method of claim 2 , further comprising performing image processing on the linearized data.

4. The method of claim 3 , wherein the image processing comprises adjusting at least one of a color, contrast, and brightness of the linearized data.

5. The method of claim 1 , wherein generating the nonlinear quantized data comprises summing the most significant bits of the linearized data with the offset, and subtracting the most significant bits of the boundary slice.

6. The method of claim 1 , further comprising:
generating a memory address based on the nonlinear quantized data; and
retrieving an output value from a lookup table that is located at the memory address.

7. The method of claim 6 , further comprising:
calculating an error of the output value;
determining the error of the output value exceeds an error tolerance; and
modifying at least one of the boundary slice, offset, and shift parameter.

8. The method of claim 6 , wherein the nonlinearized quantized data has a higher degree of precision than the memory address, the method further including generating an interpolated value based on the output value.

9. The method of claim 1 , wherein generating the most significant bits of the linearized data according to the shift parameter includes bit shifting the linearized data based on the shift parameter.

10. The method of claim 1 , wherein generating the most significant bits of the linearized data according to the shift parameter includes dividing the linearized data by a power of two indicated by the shift parameter.

11. A compressive lookup table implemented by:
at least one register for storing a boundary slice, a block bit shift, and an offset for a data block;
a compressive addressing computation processor configured to receive a linearized input data and to perform a quantization function on the linearized input data,
wherein performing a quantization function on the linearized input data comprises:
identifying the data block as containing the linearized input data;
generating most significant bits of the linearized input data according to a shift parameter of the data block;
generating most significant bits of the boundary slice of a previous data block according to the shift parameter; and
generating a nonlinear quantized data according to the most significant bits of the linearized input data, the offset, and the most significant bits of the boundary slice.

12. The compressive lookup table of claim 11 , wherein generating the nonlinear quantized data comprises summing the most significant bits of the linearized input data with the offset, and subtracting the most significant bits of the boundary slice.

13. The compressive lookup table of claim 11 comprising a lookup table for storing an output value at a memory address, the compressive lookup table further being implemented by a memory controller configured to access the memory address of the lookup table to retrieve the output value.

14. The compressive lookup table of claim 13 , wherein performing a quantization function on the linearized input data further comprises generating the memory address based on the nonlinear quantized data.

15. The compressive lookup table of claim 14 , wherein the memory controller is configured to retrieve the output value from the lookup table using the memory address.

16. The compressive lookup table of claim 15 , wherein the lookup table is configured to:
calculate an error of the output value;
determine the error of the output value exceeds an error tolerance; and
modify at least one of the boundary slice, offset, and shift parameter for the data block.

17. The compressive lookup table of claim 14 , wherein the compressive lookup table is further implemented by an integrated circuit.

18. The compressive lookup table of claim 17 , wherein the integrated circuit comprises a single memory cell corresponding to the lookup table.

19. The compressive lookup table of claim 18 , wherein the single memory cell is reprogrammable.

20. The compressive lookup table of claim 11 , wherein the at least one register comprises:
a boundary slice register for determining a boundary of the data block of the linearized input data corresponding to the linearized input data;
a block bit shift register for determining shift parameter corresponding to the data block; and
an offset register for determining an offset corresponding to the data block.

Assignees

• Samsung Display Co Ltd

Inventors

• Hoffman David M

Classifications

• G09G2320/0271

  Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping · CPC title

• H04N19/42

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title

• G09G2340/0428

  Gradation resolution change · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G09G2360/122

  Tiling · CPC title