Display device and multiplexer circuit thereof

Patent metadata

Field	Value
Publication number	US-11355045-B2
Application number	US-202117201138-A
Country	US
Kind code	B2
Filing date	Mar 15, 2021
Priority date	Mar 26, 2019
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A multiplexer circuit includes a first switch unit and a second switch unit. The first switch unit is electrically connected to a first data line and a first pixel circuit, and configured to turn on according to a first signal in a first time duration. The second switch unit is electrically connected to the first data line and a second pixel circuit, and configured to turn on according to a second signal in a second time duration. The first time duration and the second time duration substantially start or end at a same time, so that the first time duration and the second time duration have overlap.

First claim

What is claimed is:

1. A multiplexer circuit, comprising:
a first switch unit electrically connected to a first data line and a first pixel circuit, and configured to turn on according to a first signal in a first time duration; and
a second switch unit cascadingly connected to the first switch unit and electrically connected to a first data line, wherein a first node between the first switch unit and the second switch unit is directly electrically connected to a second pixel circuit, and the second switch unit is configured to turn on according to a second signal in a second time duration, wherein the first time duration and the second time duration substantially start or end at a same time, so that the first time duration and the second time duration have overlap;
wherein the multiplexer circuit is further configured to conduct the first data line to a third pixel circuit in the first time duration, the second time duration and a third time duration, and a second node between the second switch unit and the first data line is electrically connected to the third pixel circuit without a switch unit.

2. The multiplexer circuit of claim 1 , further comprising:
a third switch unit electrically connected to a second data line and a fourth pixel circuit, and configured to turn on according to the first signal in the first time duration;
a fourth switch unit cascadingly connected to the third switch unit and electrically connected to the second data line, wherein a third node between the third switch unit and the fourth switch unit is electrically connected to a fifth pixel circuit, and the fourth switch unit is configured to turn on according to the second signal.

3. The multiplexer circuit of claim 2 , wherein the multiplexer circuit is further configured to conduct the second data line to a sixth pixel circuit in the first time duration, the second time duration and a third time duration, and a fourth node between the fourth switch unit and the second data line is electrically connected to the sixth pixel circuit without a switch unit.

4. A display device, comprising:
a plurality of pixel circuits;
a first data line configured to transmit a first data voltage; and
a multiplexer circuit configured to receive the first data voltage, comprising:
a first switch unit electrically connected to a first pixel circuit of the plurality of pixel circuits, and configured to turn on according to a first signal in a first time duration; and
a second switch unit cascadingly connected to the first switch unit and electrically connected to the first data line, wherein a first node between the first switch unit and the second switch unit is directly electrically connected to a second pixel circuit of the plurality of pixel circuits, and the second switch unit is configured to turn on according to a second signal in a second time duration, wherein
the first time duration and the second time duration substantially start or end at a same time, so that the first time duration and the second time duration have overlap; wherein the multiplexer circuit is further configured to transmit a third data voltage to a third pixel circuit of the plurality of pixel circuits according to a third signal, and a second node between the second switch unit and the first data line is electrically connected to the third pixel circuit without a switch unit.

5. The display device of claim 4 , wherein the multiplexer circuit is further configured to conduct the first data line and to a third pixel circuit of the plurality of pixel circuits in the first time duration, the second time duration and a third time duration.

6. The display device of claim 4 , wherein the multiplexer circuit further comprises:
a third switch unit electrically connected to a second data line and a fourth pixel circuit of the plurality of pixel circuits, and configured to turn on according to the first signal in the first time duration; and,
a fourth switch unit cascadingly connected to the third switch unit and electrically connected to the second data line, wherein a third node between the third switch unit and the fourth switch unit is electrically connected to a fifth pixel circuit of the plurality of pixel circuits, and the fourth switch unit is configured to turn on according to the second signal.

7. The display device of claim 6 , wherein the multiplexer circuit is further configured to conduct the second data line to a sixth pixel circuit of the plurality of pixel circuits in the first time duration, the second time duration and a third time duration, and a fourth node between the fourth switch unit and the second data line is electrically connected to the sixth pixel circuit of the plurality of pixel circuits without a switch unit.

Assignees

• Au Optronics Corp

Inventors

• Lin rong-fu
• Yu Chi
• Yang Chih-Fu
• Huang Jie-Chuan
• Su Sung-Yu

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0272

  Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title