Phase synchronization updates without synchronous signal transfer

Patent metadata

Field	Value
Publication number	US-11349487-B2
Application number	US-202117218695-A
Country	US
Kind code	B2
Filing date	Mar 31, 2021
Priority date	Aug 7, 2020
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

First claim

The invention claimed is:

1. A system for generating phase updates for synchronization of integrated circuit (IC) components, the system comprising:
a phase-locked loop (PLL) circuit, configured to receive a device clock signal and generate a PLL clock signal having a frequency greater than that of the device clock signal;
a clock divider circuit, configured to generate a final digital clock signal based on the PLL clock signal;
a first phase accumulator, configured to generate a first phase update based on the final digital clock signal;
a second phase accumulator, configured to generate a second phase update based on the device clock signal, where each of the first phase update and the second phase update is indicative of an arrival of a pulse of a system reference (SYSREF) signal; and
a combiner, configured to generate the phase update based on the first phase update and the second phase update.

2. The system according to claim 1 , further comprising an input component, configured to receive the SYSREF signal and provide an output signal that includes a pulse indicative of the pulse of the SYSREF signal.

3. The system according to claim 2 , wherein the input component is a flip-flop.

4. The system according to claim 2 , further comprising a transmit copy component, configured to generate a transmit copy output indicative of a value of the second phase update at a falling edge of the pulse of the output signal of the input component.

5. The system according to claim 4 , wherein the transmit copy component includes a multiplexer and one or more flip-flops.

6. The system according to claim 4 , further comprising a state machine, configured to control operation of the transmit copy component based on the arrival of the pulse of the SYSREF signal.

7. The system according to claim 2 , further comprising a scaling component, configured to generate a scaling component output indicative of a scaled value of the second phase update at a falling edge of the pulse of the output signal of the input component, wherein the scaled value is based on a difference between the final digital clock signal and the device clock signal.

8. The system according to claim 2 , further comprising a synchronization component, configured to generate a pulse based on the pulse of the output signal of the input component, wherein the pulse generated by the synchronization component is configured to trigger provision of the second phase update to the combiner.

9. The system according to claim 2 , further comprising:
a scaling component, configured to generate a scaling component output indicative of a scaled value of the second phase update at a falling edge of the pulse of the output signal of the input component, wherein the scaled value is based on a difference between the final digital clock signal and the device clock signal; and
a synchronization component, configured to trigger provision of the scaled value to the combiner.

10. The system according to claim 2 , further comprising:
a transmit copy component, configured to generate a transmit copy output indicative of a value of the second phase update at a falling edge of the pulse of the output signal of the input component; and
a synchronization component, configured to trigger provision of a value indicative of the value of the second phase update at the falling edge of the pulse of the output signal of the input component to the combiner.

11. The system according to claim 1 , further comprising a state machine, configured to control operation of one or more of the first phase accumulator, the second phase accumulator, and the clock divider circuit based on the arrival of the pulse of the SYSREF signal.

12. The system according to claim 1 , further comprising:
a gate configured to provide the PLL clock signal to the clock divider circuit; and
a state machine configured to trigger the gate to provide the PLL clock signal to the clock divider circuit based on the arrival of the pulse of the SYSREF signal.

13. The system according to claim 1 , wherein the combiner is configured to generate the phase update by adding the first phase update and the second phase update.

14. The system according to claim 1 , wherein the first phase accumulator is a local multiframe clock.

15. The system according to claim 1 , wherein the SYSREF signal is a SYSREF signal of JESD standard.

16. The system according to claim 1 , wherein the system is a radio frequency (RF) transceiver.

17. The system according to claim 16 , wherein:
the RF transceiver further includes the IC components,
the IC components include at least one of a frequency mixer, an analog-to-digital converter, a digital-to-analog converter, an analog filter, and a digital filter, and
the RF transceiver is configured to synchronize one or more of the IC components based on the phase update generated by the combiner.

18. A timing arrangement for synchronizing one or more integrated circuit (IC) components, comprising:
a first counter, configured to count a number of cycles of a final digital clock signal, wherein the final digital clock signal is based on a phase-locked loop (PLL) clock signal, the PLL clock signal is based on a device clock signal, and a frequency of the final digital clock signal is greater than a frequency of the device clock signal;
a second counter, configured to count a number of cycles of the device clock signal; and
a phase update circuit, configured to generate a phase update indicative of an arrival of a pulse of a system reference (SYSREF) signal based on outputs of the first counter and the second counter.

19. The timing arrangement according to claim 18 , wherein the phase update circuit is configured to generate the phase update in absence of providing the SYSREF signal to the first counter.

20. The timing arrangement according to claim 18 , wherein:
the first counter is configured to count the number of cycles of the final digital clock signal by repeating a first sequence of count values,
the second counter is configured to count the number of cycles of the device clock signal by repeating a second sequence of count values, the second sequence being different from the first sequence.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Leonard Alexander
• Wu Lu
• Mayer Christopher
• Allan Gord

Classifications

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03L7/0994

  comprising an accumulator · CPC title

• H03L7/16 Primary

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title