Phase redundant power supply with ORing FET current sensing

Patent metadata

Field	Value
Publication number	US-11349381-B2
Application number	US-202016917649-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	Jun 30, 2020
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

A power stage in a multi-phase switching power supply incorporates a current sense transistor coupled in series with the output inductor to sense the phase current for the power stage. In some embodiments, the current sense transistor mirrors the output voltage disconnect transistor (the ORing FET) used to switchably connect a power stage to the output voltage node. The current sense transistor measures a portion of the inductor current flowing through the output inductor where the inductor current is indicative of the phase current of the power stage. Accurate current sensing is implemented for the power stage where the current sense value dose not require temperature compensation.

First claim

What is claimed is:

1. A power stage in a multi-phase switching power supply receiving a pulse width modulation (PWM) signal associated with a phase of the power stage and an input voltage and providing an output voltage, the power stage comprising:
a high-side power switch and a low-side power switch connected in series between an input voltage node and a ground reference voltage and controlled by the PWM signal, a switch output node between current terminals of the high-side power switch and the low-side power switch generating a switching output voltage, the switch output node being coupled to a first terminal of an output inductor;
a phase redundant controller receiving the PWM signal and generating a first control signal;
an output voltage disconnect transistor coupled between a second terminal of the output inductor and an output node providing the output voltage, the output voltage disconnect transistor receiving the first control signal from the phase redundant controller, wherein the first control signal has a first state to close the output voltage disconnect transistor to connect the output inductor to the output node and a second state to open the output voltage disconnect transistor to disconnect the output inductor from the output node; and
a current sense transistor having a first current terminal coupled to the second terminal of the output inductor and a second current terminal coupled to a first node through a sense resistor, and a control terminal receiving the first control signal, the current sense transistor having the same transistor structure as the output voltage disconnect transistor and having a size being a fraction of the output voltage disconnect transistor,
wherein the current sense transistor is turned on by the first control signal to conduct a portion of an inductor current flowing in the output inductor of the power stage, and the phase redundant controller receives a current sense voltage signal measured across the sense resistor to generate a sense current signal indicative of the inductor current.

2. The power stage of claim 1 , further comprising:
an input voltage disconnect transistor coupled between the input voltage node and the input voltage, the input voltage disconnect transistor receiving a second control signal generated by the phase redundant controller, wherein the second control signal has a first state to close the input voltage disconnect transistor to connect the high-side power switch to the input voltage and a second state to open the input voltage disconnect transistor to disconnect the high-side power switch from the input voltage.

3. The power stage of claim 1 , wherein the output voltage disconnect transistor comprises a MOS transistor and the current sense transistor comprises a MOS transistor constructed using a same transistor structure as the output voltage disconnect transistor and having a transistor channel width being a fraction of a transistor channel width of the output voltage disconnect transistor.

4. The power stage of claim 3 , wherein the output voltage disconnect transistor and the current sense transistor are formed on a same semiconductor substrate.

5. The power stage of claim 4 , wherein the output voltage disconnect transistor comprises a trench MOS transistor formed in a first plurality of trench cells and the current sense transistor comprises a trench MOS transistor formed in a second plurality of trench cells, the second plurality of trench cells being a fraction of the first plurality of trench cells.

6. The power stage of claim 5 , wherein the sense resistor is a discrete resistor provided outside of the semiconductor substrate.

7. The power stage of claim 1 , wherein the current sense transistor has a transistor channel width being 1/1000 to 1/10,000 of a transistor channel width of the output voltage disconnect transistor.

8. The power stage of claim 1 , wherein the output node of the power stage is coupled to an output capacitor of the multi-phase switching power supply to form an LC filter circuit with the output inductor in response to the output voltage disconnect transistor being closed to generate a regulated output voltage having a substantially constant magnitude at an output voltage node of the multi-phase switching power supply, the regulated output voltage being coupled to drive a load, wherein the first node comprises a node at the load for sensing the regulated output voltage provided to the load.

9. A method in a power stage of a multi-phase switching power supply receiving a pulse width modulation (PWM) signal associated with a phase of the power stage and an input voltage and providing an output voltage, the method comprising:
generating, at the power stage, a switching output voltage from the input voltage in response to the PWM signal and coupling the switching output voltage to a first terminal of an output inductor;
connecting an output voltage disconnect transistor controlled by a first control signal between a second terminal of the output inductor and an output node of the power stage providing the output voltage;
turning on the output voltage disconnect transistor in response to the first control signal to conduct an inductor current flowing in the output inductor in response to the switching output voltage;
connecting a current sense transistor controlled by the first control signal between the second terminal of the output inductor and a sense resistor, the sense resistor being connected between the current sense transistor and a first node;
conducting, at the current sense transistor, at least a portion of the inductor current flowing in the output inductor in response to the first control signal being asserted to turn on the current sense transistor and the output voltage disconnect transistor;
measuring, at the sense resistor, a current sense voltage signal indicative of a current flowing in the current sense transistor; and
providing a sense current signal in response to the current sense voltage signal, the sense current signal being indicative of the inductor current.

10. The method of claim 9 , further comprising:
connecting an input voltage disconnect transistor controlled by a second control signal between the input voltage and the power stage.

11. The method of claim 9 , wherein connecting the current sense transistor comprises:
providing the current sense transistor having a size being a fraction of the output voltage disconnect transistor.

12. The method of claim 11 , wherein connecting the current sense transistor comprises:
providing the current sense transistor having a transistor channel width being 1/1000 to 1/10,000 of a transistor channel width of the output voltage disconnect transistor.

13. The method of claim 9 , wherein connecting the current sense transistor comprises:
providing the output voltage disconnect transistor and the current sense transistor as MOS transistors having a same transistor structure, the current sense transistor having a transistor channel width being a fraction of a transistor channel width of the output voltage disconnect transistor.

14. The method of claim 9 , wherein connecting the current sense transistor comprises:
providing the output voltage disconnect transistor and the current sense transistor as trench MOS transistors having a same trench transistor structure, the output voltage disconnect transistor being formed in a first plurality of trench cells and the current sense transistor being formed in a second plurality of trench cells, the second plurality of trench cells being a fraction of the first plurality of trench cells.

15. The metho

Assignees

• Alpha & Omega Semiconductor Int Lp

Inventors

• Upadhyaya Prabal

Classifications

• G06F1/206

  comprising thermal management · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/0009 Primary

  Devices or circuits for detecting current in a converter · CPC title

• H02M3/1586

  switched with a phase shift, i.e. interleaved · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title