Array substrate, method for fabricating the same, and display device

Patent metadata

Field	Value
Publication number	US-11347334-B2
Application number	US-201816471393-A
Country	US
Kind code	B2
Filing date	Dec 4, 2018
Priority date	Mar 30, 2018
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

An array substrate, a method for fabricating the same, and a display device are provided. The array substrate includes: a base substrate; touch electrode wiring including a first conductive layer and a second conductive layer, where the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer includes at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer; a planarization layer on the second conductive layer, where the planarization layer includes at least one first touch electrode contact hole; and touch electrode on the planarization layer, where the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.

First claim

The invention claimed is:

1. An array substrate, comprising:
a base substrate;
touch electrode wiring comprising a first conductive layer and a second conductive layer, wherein the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer comprises at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer;
a planarization layer on a side of the second conductive layer away from the base substrate, wherein the planarization layer comprises at least one first touch electrode contact hole, and an orthographic projection of the first touch electrode contact hole on the base substrate covers an orthographic projection of the first via hole on the base substrate; and
at least one touch electrode on a side of the planarization layer away from the base substrate, wherein the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.

2. The array substrate according to claim 1 , wherein the first conductive layer comprises at least one groove,
wherein an orthographic projection of the groove on the base substrate overlaps with the orthographic projection of the first via hole on the base substrate.

3. The array substrate according to claim 1 , further comprising:
a first passivation layer between the touch electrode and the planarization layer, wherein the first passivation layer comprises at least one second touch electrode contact hole;
an area of an orthographic projection of the second touch electrode contact hole on the base substrate is smaller than an area of the orthographic projection of the first touch electrode contact hole on the base substrate; and
the touch electrode is connected with the first conductive layer through the first touch electrode contact hole, the second touch electrode contact hole, and the first via hole.

4. The array substrate according to claim 3 , further comprising: at least one driver transistor for driving at least one pixel electrode, wherein:
the touch electrode wiring is arranged at a same layer as the driver transistor and insulated from source and drain electrodes of the driver transistor.

5. The array substrate according to claim 4 , wherein the second conductive layer further comprises at least one second via hole, and the planarization layer further comprises at least one first pixel electrode contact hole, wherein:
an orthographic projection of the first pixel electrode contact hole on the base substrate covers an orthographic projection of the second via hole on the base substrate.

6. The array substrate according to claim 5 , further comprising: at least one touch electrode block at least located in the at least one second via hole, wherein:
the touch electrode block is arranged at a same layer as the touch electrode.

7. The array substrate according to claim 6 , wherein the first passivation layer further comprises at least one second pixel electrode contact hole, wherein:
an area of an orthographic projection of the second pixel electrode contact hole on the base substrate is smaller than an area of the orthographic projection of the first pixel electrode contact hole on the base substrate; and
the pixel electrode is connected with the touch electrode block through the first pixel electrode contact hole, the second pixel electrode contact hole, and the second via hole.

8. The array substrate according to claim 6 , further comprising a second passivation layer between the touch electrode and the pixel electrode, wherein:
an orthographic projection of the second passivation layer on the base substrate does not overlap with the orthographic projection of the first pixel electrode contact hole on the base substrate.

9. A display device, comprising the array substrate according to claim 1 .

10. A method for fabricating an array substrate, comprising:
preparing a base substrate;
forming touch electrode wiring on the base substrate, the touch electrode wiring comprising a first conductive layer and a second conductive layer, wherein the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer comprises at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer;
forming a planarization layer on a side of the second conductive layer away from the base substrate, wherein the planarization layer comprises at least one first touch electrode contact hole, and an orthographic projection of the first touch electrode contact hole on the base substrate covers an orthographic projection of the first via hole on the base substrate; and
forming at least one touch electrode on a side of the planarization layer away from the base substrate, wherein the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.

11. The method according to claim 10 , wherein before the touch electrode is formed, the method further comprises:
forming a first passivation layer on the side of the planarization layer away from the base substrate, wherein:
the first passivation layer comprises at least one second touch electrode contact hole;
an area of an orthographic projections of the second touch electrode contact hole on the base substrate is smaller than an area of an orthographic projection of the first touch electrode contact hole on the base substrate; and
the touch electrode is connected with the first conductive layer through the first touch electrode contact hole, the second touch electrode contact hole, and the first via hole.

12. The method according to claim 10 , wherein after the first touch electrode contact hole is formed, the method further comprises:
removing the second conductive layer in position corresponding to the first touch electrode contact hole to form the first via hole to expose the first conductive layer.

13. The method according to claim 10 , wherein when the first touch electrode contact hole is formed in the planarization layer, the method further comprises:
forming at least one first pixel electrode contact hole in the planarization layer in a same patterning process as the first touch electrode contact hole.

14. The method according to claim 13 , wherein after the first pixel electrode contact hole is formed, the method further comprises:
removing the second conductive layer in position corresponding to the first pixel electrode contact hole to form second via hole to expose the first conductive layer.

15. The method according to claim 14 , wherein when the touch electrode is formed on the side of the planarization layer away from the base substrate, the method further comprises:
forming a touch electrode block in the second via hole in a same patterning process as the touch electrode.

16. The method according to claim 15 , wherein after the touch electrode is formed on the side of the planarization layer away from the base substrate, the method further comprises:
forming a second passivation layer on a side of the touch electrode away from the base substrate, wherein an orthographic projection of the second passivation layer on the base substrate does not overlap with the orthographic projection of the first pixel electrode contact hole on the base substrate.

17. The method according to claim 16 , wherein after the second p

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Duan Cenhong
• Shi Dawei
• Wang Fengguo
• Li Feng
• Liu Hong
• Wu Xinguo
• Yang Lu
• Wang Wentao
• Wang Zifeng
• Ma Bo
• Li Yuanbo
• Guo Zhixuan
• Zhao Jing
• Liang Haiqin

Classifications

• G06F2203/04103

  Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

• G06F3/0443

  using a single layer of sensing electrodes · CPC title

• G06F3/0412 Primary

  Digitisers structurally integrated in a display · CPC title

• G06F3/04164

  Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title

• G06F3/044

  by capacitive means · CPC title