Die for a printhead

Patent metadata

Field	Value
Publication number	US-11345145-B2
Application number	US-201916766521-A
Country	US
Kind code	B2
Filing date	Feb 6, 2019
Priority date	Feb 6, 2019
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

A die for a printhead is provided in examples. The die includes a number of fluidic actuator arrays, proximate to a number of fluid feed holes. A number of address lines are disposed proximate to a number of logic circuits on a low-voltage side of the fluid feed holes. An address decoder circuit is coupled to at least a portion of the address lines to select a fluidic actuator in a fluidic actuator array for firing. The address decoder circuit is customized to select a different address for each fluidic actuator in the fluidic actuator array. A logic circuit triggers a driver circuit located in a high-voltage side of the plurality of fluid feed holes opposite the low-voltage side, based, at least in part, on a bit value for the fluidic actuator array, the fluidic actuator selected by the address decoder circuit, and a firing signal.

First claim

What is claimed is:

1. A die for a printhead, comprising:
a plurality of fluidic actuator arrays, proximate to a plurality of fluid feed holes;
a plurality of address lines, proximate to a plurality of logic circuits on a low-voltage side of the plurality of fluid feed holes; and
an address decoder circuit that couples to at least a portion of the address lines to select a fluidic actuator in a fluidic actuator array for firing, wherein the address decoder circuit is customized to select a different address for each fluidic actuator in the fluidic actuator array; and
a logic circuit that triggers a driver circuit located in a high-voltage side of the plurality of fluid feed holes opposite the low-voltage side, based, at least in part, on a bit value for the fluidic actuator array, the fluidic actuator selected by the address decoder circuit, and a firing signal.

2. The die of claim 1 , comprising a sense bus communicatively coupled to a multiplexer that communicatively couples a selected thermal sensor from the group to the sense bus.

3. The die of claim 1 , comprising a high-voltage protection switch configured to isolate a sense bus from a memory bus.

4. The die of claim 1 , comprising a memory voltage regulator to generate a high-voltage potential to program memory bits on the memory bus.

5. The die of claim 1 , comprising a common firing line to trigger a fluidic actuator selected in the fluidic actuator array to fire.

6. The die of claim 1 , wherein the plurality of fluidic actuator arrays comprises two virtual columns.

7. The die of claim 1 , comprising a memory element for each fluidic actuator array in the plurality of fluidic actuator arrays.

8. The die of claim 1 , wherein the die is less than about 750 micrometers in width, and wherein the plurality of fluid feed holes opens to a back face of the die to receive fluid and provide the fluid to the plurality of fluidic actuator arrays on a front face of the die.

9. The die of claim 1 , wherein the address decoder circuit comprises a plurality of vias that couple the portion of the address lines to the logic circuit.

10. The die of claim 1 , wherein the address decoder circuit comprises a single logic block for a fluidic actuator array.

11. The die of claim 1 , wherein the address decoder circuit comprises connections from the logic circuit to field-effect transistors (FETs) that enable the fluidic actuators of the fluidic actuator array, and wherein the connections are mapped during initial fabrication of the die.

12. A method for forming a die for a printhead, comprising:
etching a plurality of fluid feed holes in a line down a substrate;
depositing a plurality of layers on the substrate to form:
a plurality of fluidic actuator arrays, proximate to the plurality of fluid feed holes;
a plurality of address lines, proximate to a plurality of logic circuits in a low-voltage region disposed on one side of the plurality of fluid feed holes;
an address decoder circuit that couples to at least a portion of the plurality of address lines to select a fluidic actuator in a fluidic actuator array for firing, wherein the address decoder circuit is customized to select a different address for each fluidic actuator in the fluidic actuator array; and
a logic circuit in the plurality of logic circuits that triggers a driver circuit located in a high-voltage region on an opposite side of the plurality of fluid feed holes based, at least in part, on a bit value for the fluidic actuator array, the fluidic actuator selected by the address decoder circuit, and a firing signal.

13. The method of claim 12 , comprising forming a plurality of vias in a post processing operation after the plurality of layers are formed on the substrate, wherein the plurality of vias electrically couple the portion of the plurality of address lines to the address decoder circuit.

14. The method of claim 12 , comprising depositing layers to form a single logic block for selecting a fluidic actuator in the fluidic actuator array.

15. The method of claim 12 , comprising depositing layers to form mapped power connections from the logic circuit to a field-effect transistor (FET) that power a fluidic actuator in the fluidic actuator array.

16. A printhead comprising a die, comprising:
a plurality of fluidic actuator arrays, proximate to a plurality of fluid feed holes;
a plurality of address lines, proximate to a plurality of logic circuits in a low-voltage region disposed on one side of the plurality of fluid feed holes;
a plurality of address bits, wherein each address bit sets a value of one of the plurality of address lines; and
an address decoder circuit that couples to at least a portion of the address lines to select a fluidic actuator in a fluidic actuator array for firing, wherein the address decoder circuit is customized to select a different address for each fluidic actuator in the fluidic actuator array; and
a logic circuit in the plurality of logic circuits that triggers a driver circuit located in a high-voltage region on an opposite side of the plurality of fluid feed holes based, at least in part, on a bit value for the fluidic actuator array, the fluidic actuator selected by the address decoder circuit, and a firing signal.

17. The printhead of claim 16 , comprising a polymeric mount holding the die, wherein the polymeric mount comprises a slot disposed along a back face of the die to provide fluid from a fluid reservoir to the plurality of fluid feed holes.

18. The printhead of claim 16 , comprising a plurality of vias to electrically couple the portion of the plurality of address lines to the address decoder circuit.

19. The printhead of claim 16 , comprising a single logic block for selecting a fluidic actuator in the fluidic actuator array.

20. The printhead of claim 16 , comprising mapped power connections from the logic circuit to a field-effect transistor (FET) that power a fluidic actuator in the fluidic actuator array.

Assignees

• Hewlett Packard Development Co

Inventors

• Martin Eric
• Linn Scott A
• Gardner James Michael

Classifications

• B41J2/04541 Primary

  Specific driving circuit · CPC title

• B41J2/14072

  Electrical connections, e.g. details on electrodes, connecting the chip to the outside... · CPC title

• B41J2/1626

  etching · CPC title

• B41J2/04543 Primary

  Block driving · CPC title

• B41J2/1607

  Production of print heads with piezoelectric elements (B41J2/1606, B41J2/162 take precedence) · CPC title