Technologies for quality of service based throttling in fabric architectures

Patent metadata

Field	Value
Publication number	US-11343177-B2
Application number	US-202017086320-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	Apr 1, 2016
Publication date	May 24, 2022
Grant date	May 24, 2022

Abstract

Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

First claim

The invention claimed is:

1. An apparatus comprising:
a first multi-chip package comprising:
a first plurality of cores;
a first interconnect coupled to the first plurality of cores;
an interconnect link to transmit data;
a second interconnect coupled to the first interconnect via the interconnect link;
a first memory interconnect to couple the first plurality of cores to a first system memory device, the first plurality of cores to access the first memory interconnect via the first interconnect, the interconnect link, and the second interconnect;
wherein the first memory interconnect and first system memory device are to be associated with a first non-uniform memory access (NUMA) domain;
wherein the first multi-chip package is coupled to a second multi-chip package associated with a second NUMA domain;
wherein a first NUMA domain identifier is to be associated with the first NUMA domain and a second NUMA domain identifier is to be associated with the second NUMA domain;
monitoring circuitry for monitoring utilization of a resource associated with the first NUMA domain, the monitoring circuitry including one or more model-specific registers (MSRs) to store counter values associated with requests to access the resource,
the counter values including a first counter value associated with utilization of a first resource from within the first NUMA domain and a second counter value associated with utilization of the first resource from at least the second NUMA domain; and
enforcement circuitry for limiting utilization of the first resource from within the first NUMA domain or from the second NUMA domain in accordance with one or more of the counter values.

2. The apparatus of claim 1 further comprising a general purpose central processing unit (CPU).

3. The apparatus of claim 1 further comprising a plurality of cache levels including a level 1 (L1) cache.

4. The apparatus of claim 1 further comprising a control channel to be formed between the first multi-chip package and the second multi-chip package, the control channel to carry control messages to indicate operational modifications to one or more execution resources of the first plurality of cores.

5. The apparatus of claim 1 further comprising an IO interface to couple the first plurality of cores to one or more IO devices.

6. The apparatus of claim 1 further comprising an inter-socket interconnect to couple the second interconnect to a second plurality of dies of the second multi-chip package, wherein the second plurality of dies is associated with the second NUMA domain.

7. The apparatus of claim 1 wherein the first multi-chip package comprises a first plurality of chips and wherein a first chip of the first plurality of chips comprises the first plurality of cores and the first interconnect.

8. The apparatus of claim 1 wherein the interconnect link is a multi-protocol interconnect link to transmit data in accordance with a plurality of protocols including a memory protocol.

9. The apparatus of claim 1 wherein a second chip of the first plurality of chips comprising the second interconnect and the first memory interconnect.

10. The apparatus of claim 9 wherein the second chip further comprises an IO interface to couple the first plurality of cores to one or more TO devices.

11. A system comprising:
a first system memory device;
a second system memory device; and
a first multi-chip package coupled to the first system memory device, the first multi-chip package comprising:
a first plurality of cores; and
a first interconnect coupled to the first plurality of cores;
an interconnect link to transmit data;
a second interconnect coupled to the first interconnect via the interconnect link,
a first memory interconnect to couple the first plurality of cores to the first system memory device, the first plurality of cores to access the first memory interconnect via the first interconnect, the interconnect link, and the second interconnect;
wherein the first memory interconnect and first system memory device are to be associated with a first non-uniform memory access (NUMA) domain;
wherein the first multi-chip package is coupled to a second multi-chip package, the second multi-chip package coupled to the second system memory device and associated with a second NUMA domain;
wherein a first NUMA domain identifier is to be associated with the first NUMA domain and a second NUMA domain identifier is to be associated with the second NUMA domain; and
monitoring circuitry for monitoring utilization of a resource associated with the first NUMA domain, the monitoring circuitry including one or more model-specific registers (MSRs) to store counter values associated with requests to access the resource,
the counter values including a first counter value associated with utilization of a first resource from within the first NUMA domain and a second counter value associated with utilization of the first resource from at least the second NUMA domain; and
enforcement circuitry for limiting utilization of the first resource from within the first NUMA domain or from the second NUMA domain in accordance with one or more of the counter values.

12. The system of claim 11 further comprising a general purpose central processing unit (CPU).

13. The system of claim 11 further comprising a plurality of cache levels including a level 1 (L1) cache.

14. The system of claim 11 further comprising a control channel to be formed between the first multi-chip package and the second multi-chip package, the control channel to carry control messages to indicate operational modifications to one or more execution resources of the first plurality of cores.

15. The system of claim 11 further comprising an IO interface to couple the first plurality of cores to one or more IO devices.

16. The system of claim 11 further comprising an inter-socket interconnect to couple the second interconnect to a second plurality of dies of the second multi-chip package, wherein the second plurality of dies is associated with the second NUMA domain.

17. The system of claim 11 wherein the first multi-chip package comprises a first plurality of chips and wherein a first chip of the first plurality of chips comprises the first plurality of cores and the first interconnect.

18. The system of claim 11 wherein the interconnect link is a multi-protocol interconnect link to transmit data in accordance with a plurality of protocols including a memory protocol.

19. The system of claim 11 wherein a second chip of the first plurality of chips comprising the second interconnect and the first memory interconnect.

20. The system of claim 19 wherein the second chip further comprises an TO interface to couple the first plurality of cores to one or more TO devices.

21. A method comprising:
providing a first multi-chip package comprising: a first plurality of cores; a first interconnect coupled to the first plurality of cores; an interconnect link to transmit data; a second interconnect coupled to the first interconnect via the interconnect link; a first memory interconnect to couple the first plurality of cores to a first system memory device, the first plurality of cores to access the first memory interconnect via the first interconnect, the interconnect link, and the second interconnect;
associating the first memory interconnect and first system memory device with a first non-uniform memory access (NUMA) domain, wherein the first multi-chip package is coupled to a second multi-chip pack

Assignees

• Guim Bernat Francesc
• Kumar Karthik
• Willhalm Thomas
• Ramanujan Raj
• Slechta Brian
• Intel Corp

Inventors

• Guim Bernat Francesc
• Kumar Karthik
• Willhalm Thomas
• Ramanujan Raj
• Slechta Brian

Classifications

• H04L49/205

  Quality of Service based · CPC title

• H04L47/24

  Traffic characterised by specific attributes, e.g. priority or QoS · CPC title

• H04L47/125

  by balancing the load, e.g. traffic engineering · CPC title

• H04L49/103

  using a shared central buffer; using a shared memory · CPC title

• H04L49/15 Primary

  Interconnection of switching modules · CPC title